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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id x1sm289697pfj.95.2021.01.11.10.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 10:16:48 -0800 (PST) Date: Mon, 11 Jan 2021 11:16:46 -0700 From: Mathieu Poirier To: Leo Yan Subject: Re: [PATCH v1 0/7] coresight: etm-perf: Fix pid tracing with VHE Message-ID: <20210111181646.GB144935@xps15> References: <20210109074435.626855-1-leo.yan@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210109074435.626855-1-leo.yan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210111_131652_107106_462DAD3B X-CRM114-Status: GOOD ( 33.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Denis Nikitin , Suzuki K Poulose , Alexander Shishkin , Jiri Olsa , coresight@lists.linaro.org, John Garry , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Daniel Kiss , Will Deacon , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Leo, Suzuki and Mike have pointed out a few things to modify and there was a couple of kernel bot warnings to address as well. As such I will wait for your next revision before looking at this set. Thanks, Mathieu On Sat, Jan 09, 2021 at 03:44:28PM +0800, Leo Yan wrote: > This patch series is a following up for the previous version which was > delivered by Suzuki [1]. Below gives the background info for why we > need this patch series, directly quotes the description in the cover > letter of the previous version: > > "With the Virtualization Host Extensions, the kernel can run at EL2. > In this case the pid is written to CONTEXTIDR_EL2 instead of the > CONTEXTIDR_EL1. Thus the normal coresight tracing will be unable > to detect the PID of the thread generating the trace by looking > at the CONTEXTIDR_EL1. Thus, depending on the kernel EL, we must > switch to tracing the correct CONTEXTIDR register. > > With VHE, we must set the TRCCONFIGR.VMID and TRCCONFIGR.VMID_OPT > to include the CONTEXTIDR_EL2 as the VMID in the trace. This > requires the perf tool to detect the changes in the TRCCONFIGR and > use the VMID / CID field for the PID. The challenge here is for > the perf tool to detect the kernel behavior. > > Instead of the previously proposed invasive approaches, this set > implements a less intrusive mechanism, by playing with the > perf_event.attribute.config bits." > > Same as the previous series, this series keeps the same implementation > for two introduced format bits: > > - contextid_in_vmid -> Is only supported when the VMID tracing > and CONTEXTIDR_EL2 both are supported. When requested the perf > etm4x backend sets (TRCCONFIGR.VMID | TRCCONFIGR.VMID_OPT). > As per ETMv4.4 TRM, when the core supports VHE, the CONTEXTIDR_EL2 > tracing is mandatory. (See the field TRCID2.VMIDOPT) > > - pid -> Is an alias for the correct config to enable PID tracing > on any kernel. > i.e, in EL1 kernel -> pid == contextid > EL2 kernel -> pid == contextid_in_vmid > > With this, the perf tool is also updated to request the "pid" > tracing whenever available, falling back to "contextid" if it > is unavailable. > > Comparing against the old version, this patch series uses the metadata > to save PID format; after add new item into metadata, it introduces > backward compatibility issue. To allow backward compatibility, this > series calculates per CPU metadata array size and avoid to use the > defined macro, so can always know the correct array size based on the > info stored in perf data file. Finally, the PID format stored in > metadata is passed to decoder and guide the decoder to set PID from > CONTEXTIDR_EL1 or VMID. > > This patch series has been tested on Arm Juno-r2 board, with testing > two perf data files: one data file is recorded by the latest perf tool > after applied this patch series, and another data file is recorded by > old perf tool without this patch series, so this can prove the tool is > backward compatible. > > Changes from RFC: > * Added comments to clarify cases requested (Leo); > * Explain the change to generic flags for cs_etm_set_option() in the > commit description; > * Stored PID format in metadata and passed it to decoder (Leo); > * Enhanced cs-etm for backward compatibility (Denis Nikitin). > > [1] https://archive.armlinux.org.uk/lurker/message/20201110.183310.24406f33.en.html > > > Leo Yan (4): > perf cs-etm: Calculate per CPU metadata array size > perf cs-etm: Add PID format into metadata > perf cs-etm: Fixup PID_FMT when it is zero > perf cs-etm: Add helper cs_etm__get_pid_fmt() > > Suzuki K Poulose (3): > coresight: etm-perf: Add support for PID tracing for kernel at EL2 > perf cs_etm: Use pid tracing explicitly instead of contextid > perf cs-etm: Detect pid in VMID for kernel running at EL2 > > .../hwtracing/coresight/coresight-etm-perf.c | 14 +++ > .../coresight/coresight-etm4x-core.c | 9 ++ > include/linux/coresight-pmu.h | 11 ++- > tools/include/linux/coresight-pmu.h | 11 ++- > tools/perf/arch/arm/util/cs-etm.c | 89 +++++++++++++++---- > .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 32 ++++++- > tools/perf/util/cs-etm.c | 61 ++++++++++++- > tools/perf/util/cs-etm.h | 3 + > 8 files changed, 198 insertions(+), 32 deletions(-) > > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel