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Tue, 12 Jan 2021 00:58:31 -0800 (PST) Date: Tue, 12 Jan 2021 16:58:26 +0800 From: Leo Yan To: Mike Leach Subject: Re: [PATCH v1 1/7] coresight: etm-perf: Add support for PID tracing for kernel at EL2 Message-ID: <20210112085826.GC18965@leoy-ThinkPad-X240s> References: <20210109074435.626855-1-leo.yan@linaro.org> <20210109074435.626855-2-leo.yan@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210112_035834_857891_216897F9 X-CRM114-Status: GOOD ( 20.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Al Grant , Denis Nikitin , Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Jiri Olsa , Coresight ML , John Garry , Linux Kernel Mailing List , Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Will Deacon , linux-arm-kernel , Daniel Kiss Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, On Mon, Jan 11, 2021 at 04:22:39PM +0000, Mike Leach wrote: [...] > > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > > index b0e35eec6499..927c6285ce5d 100644 > > --- a/include/linux/coresight-pmu.h > > +++ b/include/linux/coresight-pmu.h > > @@ -11,16 +11,19 @@ > > #define CORESIGHT_ETM_PMU_SEED 0x10 > > > > /* ETMv3.5/PTM's ETMCR config bit */ > > -#define ETM_OPT_CYCACC 12 > > -#define ETM_OPT_CTXTID 14 > > -#define ETM_OPT_TS 28 > > -#define ETM_OPT_RETSTK 29 > > +#define ETM_OPT_CYCACC 12 > > +#define ETM_OPT_CTXTID 14 > > +#define ETM_OPT_CTXTID_IN_VMID 15 > > Minor issue here - ETMv3.x / PTM cannot trace CXTID in VMID so this > may better be named ETM4_OPT_CTXTID_IN_VMID, rather than be grouped > with the ETM3.5 options? I looked into this suggestion but found it's complex than I assumed. This config bits are not only used for ETMv3.x / PTM, it's also used as an configuration interface between user space in Perf and kernel drivers. For example, in the userspace, perf tool sets bit ETM_OPT_TS to enable timestamp [1], this is same for ETMv3 and ETMv4. In the kernel side, the configuration is directly used ETMv3 (in coresight-etm3x-core.c), but the configuration bits are converted for ETMv4 in the function etm4_parse_event_config() [2]. So this is a historical issue, at the early period ETMv3 and ETMv4 can be compatible with each other for configurations, but after evoluation, some configs only belong to ETMv4 and cannot be applied on ETMv3 anymore, but we still use ETMv3.5 config bits as the interface between kernel and userspace. I'd like suggest we use a saperate patch set to refactor the configuration bits, e.g. define the arbitrary configuration bits as interface between user space and kernel, these bits are neutral for any ETM version, in the kernel ETM drivers need to convert to its own configuration formats. For this patch, I want to keep current change as it is, is this okay for you? Thanks, Leo [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm/util/cs-etm.c?h=v5.11-rc3#n152 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/hwtracing/coresight/coresight-etm4x-core.c?h=v5.11-rc3#n422 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel