From: Vinod Koul <vkoul@kernel.org>
To: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/6] STM32 USBPHYC PLL management rework
Date: Wed, 13 Jan 2021 20:40:33 +0530 [thread overview]
Message-ID: <20210113151033.GU2771@vkoul-mobl> (raw)
In-Reply-To: <20210105090525.23164-1-amelie.delaunay@foss.st.com>
On 05-01-21, 10:05, Amelie Delaunay wrote:
> STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
> supplies. To ensure a good behavior of the PLL, during boot, runtime and
> suspend/resume sequences, this series reworks its management to fix regulators
> issues and improve PLL status reliability.
Applied, thanks
--
~Vinod
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prev parent reply other threads:[~2021-01-13 15:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 9:05 [PATCH v2 0/6] STM32 USBPHYC PLL management rework Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 1/6] dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 2/6] phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 3/6] phy: stm32: replace regulator_bulk* by multiple regulator_* Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 4/6] phy: stm32: ensure pll is disabled before phys creation Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 5/6] phy: stm32: ensure phy are no more active when removing the driver Amelie Delaunay
2021-01-05 9:05 ` [PATCH v2 6/6] phy: stm32: rework PLL Lock detection Amelie Delaunay
2021-01-13 15:10 ` Vinod Koul [this message]
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