From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 489B7C433E0 for ; Wed, 13 Jan 2021 18:14:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D0F6F23120 for ; Wed, 13 Jan 2021 18:14:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D0F6F23120 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=e9bn8EK+sJtlV33K/TihmYKz6HQoY+2oUkcLwUUtEkE=; b=eEc5eqtT24Gwl6BmNsYbpMORM s2O3qSkOFoKCf9rqP9e2lx/sh5xhgi7Ht9SV7BFfq3W0f+V/vZYnz6I9NCeEA8GcKODe2rVjUomBx MgYh2gIXvT4s2f0pQ/Qyibh5AoyEuRCQkWrPIft0uLcjtTg9L8rZdYQDo5PD1QpdTSt6se7gtMr+b C1fifegVZ6KSQP1DLdDHzMS84LUaWoUC+NUr3BfLHTyPDH6MYtsD14zaMBGW+3eeRsB1cl6T/Fs55 kdCMMwBfFxSdRhhN1L1Ew97YxoTaywyfKbRe7je8yE4gRkxweR6wb7IpBK0PeeGXVCYSDn4rn7dxB /pyQ0fMag==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kzkcG-0007zm-BY; Wed, 13 Jan 2021 18:11:32 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kzkcB-0007yr-Ms for linux-arm-kernel@lists.infradead.org; Wed, 13 Jan 2021 18:11:30 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7D14C233ED; Wed, 13 Jan 2021 18:11:24 +0000 (UTC) Date: Wed, 13 Jan 2021 18:11:21 +0000 From: Catalin Marinas To: Vincenzo Frascino Subject: Re: [PATCH v2 3/4] arm64: mte: Enable async tag check fault Message-ID: <20210113181121.GF27045@gaia> References: <20210107172908.42686-1-vincenzo.frascino@arm.com> <20210107172908.42686-4-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210107172908.42686-4-vincenzo.frascino@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210113_131127_895855_2A403C13 X-CRM114-Status: GOOD ( 24.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Branislav Rankov , Marco Elver , Andrey Konovalov , Evgenii Stepanov , linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Alexander Potapenko , linux-arm-kernel@lists.infradead.org, Andrey Ryabinin , Will Deacon , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 07, 2021 at 05:29:07PM +0000, Vincenzo Frascino wrote: > diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h > index d02aff9f493d..a60d3718baae 100644 > --- a/arch/arm64/include/asm/mte.h > +++ b/arch/arm64/include/asm/mte.h > @@ -39,6 +39,7 @@ void mte_free_tag_storage(char *storage); > /* track which pages have valid allocation tags */ > #define PG_mte_tagged PG_arch_2 > > +void mte_check_tfsr_el1(void); > void mte_sync_tags(pte_t *ptep, pte_t pte); > void mte_copy_page_tags(void *kto, const void *kfrom); > void flush_mte_state(void); > @@ -56,6 +57,9 @@ void mte_assign_mem_tag_range(void *addr, size_t size); > /* unused if !CONFIG_ARM64_MTE, silence the compiler */ > #define PG_mte_tagged 0 > > +static inline void mte_check_tfsr_el1(void) > +{ > +} I think we should enable this dummy function when !CONFIG_KASAN_HW_TAGS. It saves us an unnecessary function call in a few places. > static inline void mte_sync_tags(pte_t *ptep, pte_t pte) > { > } > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > index 5346953e4382..74b020ce72d7 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -37,6 +37,8 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) > lockdep_hardirqs_off(CALLER_ADDR0); > rcu_irq_enter_check_tick(); > trace_hardirqs_off_finish(); > + > + mte_check_tfsr_el1(); > } > > /* > @@ -47,6 +49,8 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *regs) > { > lockdep_assert_irqs_disabled(); > > + mte_check_tfsr_el1(); > + > if (interrupts_enabled(regs)) { > if (regs->exit_rcu) { > trace_hardirqs_on_prepare(); > @@ -243,6 +247,8 @@ asmlinkage void noinstr enter_from_user_mode(void) > > asmlinkage void noinstr exit_to_user_mode(void) > { > + mte_check_tfsr_el1(); While for kernel entry the asynchronous faults are sync'ed automatically with TFSR_EL1, we don't have this for exit, so we'd need an explicit DSB. But rather than placing it here, it's better if we add a bool sync argument to mte_check_tfsr_el1() which issues a dsb() before checking the register. I think that's the only place where such argument would be true (for now). > + > trace_hardirqs_on_prepare(); > lockdep_hardirqs_on_prepare(CALLER_ADDR0); > user_enter_irqoff(); > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 5d992e16b420..26030f0b79fe 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -185,6 +185,34 @@ void mte_enable_kernel(enum kasan_arg_mode mode) > isb(); > } > > +void mte_check_tfsr_el1(void) > +{ > + u64 tfsr_el1; > + > + if (!IS_ENABLED(CONFIG_KASAN_HW_TAGS)) > + return; If we define the static inline when !CONFIG_KASAN_HW_TAGS, we could add the #ifdef here around the whole function. > + if (!system_supports_mte()) > + return; > + > + tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1); > + > + /* > + * The kernel should never hit the condition TF0 == 1 > + * at this point because for the futex code we set > + * PSTATE.TCO. > + */ > + WARN_ON(tfsr_el1 & SYS_TFSR_EL1_TF0); > + > + if (tfsr_el1 & SYS_TFSR_EL1_TF1) { > + write_sysreg_s(0, SYS_TFSR_EL1); > + isb(); > + > + pr_err("MTE: Asynchronous tag exception detected!"); > + } > +} > +NOKPROBE_SYMBOL(mte_check_tfsr_el1); Do we need this to be NOKPROBE_SYMBOL? It's not that low level. > + > static void update_sctlr_el1_tcf0(u64 tcf0) > { > /* ISB required for the kernel uaccess routines */ > @@ -250,6 +278,15 @@ void mte_thread_switch(struct task_struct *next) > /* avoid expensive SCTLR_EL1 accesses if no change */ > if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) > update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); > + > + /* > + * Check if an async tag exception occurred at EL1. > + * > + * Note: On the context switch patch we rely on the dsb() present s/patch/path/ > + * in __switch_to() to guaranty that the indirect writes to TFSR_EL1 s/guaranty/guarantee/ (well, still valid though I think rarely used). > + * are synchronized before this point. > + */ > + mte_check_tfsr_el1(); > } > > void mte_suspend_exit(void) > -- > 2.30.0 -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel