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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id 8sm1276191oii.45.2021.01.14.12.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 12:11:27 -0800 (PST) Received: (nullmailer pid 3509247 invoked by uid 1000); Thu, 14 Jan 2021 20:11:26 -0000 Date: Thu, 14 Jan 2021 14:11:26 -0600 From: Rob Herring To: Samuel Holland Subject: Re: [PATCH v4 01/10] dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi Message-ID: <20210114201126.GA3509187@robh.at.kernel.org> References: <20210112055950.21209-1-samuel@sholland.org> <20210112055950.21209-2-samuel@sholland.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210112055950.21209-2-samuel@sholland.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210114_151129_717050_9555D6ED X-CRM114-Status: GOOD ( 17.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, Jernej Skrabec , Marc Zyngier , linux-kernel@vger.kernel.org, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Thomas Gleixner , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 11 Jan 2021 23:59:41 -0600, Samuel Holland wrote: > The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional > functionality compared to the sun7i/sun9i NMI controller. Among other > things, it multiplexes access to up to 128 interrupts corresponding to > (and in parallel to) the first 128 GIC SPIs. This means the NMI is no > longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or > 96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0. > > To allow access to all multiplexed IRQs, the R_INTC requires a new > binding where the interrupt number matches the GIC interrupt number. > Otherwise, interrupts with hwirq numbers below the NMI would not be > representable in the device tree. > > For simplicity, copy the three-cell GIC binding; this disambiguates > interrupt 0 in the old binding (the NMI) from interrupt 0 in the new > binding (SPI 0) by the number of cells. > > Because the H6 R_INTC has a different mapping from multiplexed IRQs to > top-level register bits, it is no longer compatible with the A31 R_INTC. > > Signed-off-by: Samuel Holland > --- > .../allwinner,sun6i-a31-r-intc.yaml | 66 +++++++++++++++++++ > .../allwinner,sun7i-a20-sc-nmi.yaml | 10 --- > 2 files changed, 66 insertions(+), 10 deletions(-) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml > Reviewed-by: Rob Herring _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel