From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C619C433DB for ; Tue, 19 Jan 2021 20:38:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3824123107 for ; Tue, 19 Jan 2021 20:38:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3824123107 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=88zd6vp0jfa9gyw1zzHxrPcW+na63UgIf9qck8BtMUs=; b=HDE7JaSrI5+W0VCfpcc4z0Eh9 yHZvfueM1xv6F1xrJqfm2oibjKt+O8IyHog+wA1XZAABiPG64YC+kvWYojxAlsVDEimSnKWcF/uK7 SNsQrwhOoIM5OsRUr4yNQB6gQ6TBLmh54a7VmTGGw98qkqP5hdeU/lXfOYOLJAlrBvaVvpyn57q5I BMNbeYxnDeeC7U8aBvYd0HBG5mzJT9Ck9JXaB857C6qTSt/iINh2+ushHKLrqmgmyGAh2lxOqQzkX vpGfXdXZQfY/W4OnhSon1Zx2lfVnEEV81AUZaspNaGkeepDQh1mUuUXG5gydtU5AdXk0KfEjeL5Bn pEeNB7S2w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1xkd-0000rE-Uz; Tue, 19 Jan 2021 20:37:19 +0000 Received: from relay6-d.mail.gandi.net ([217.70.183.198]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1xkb-0000qm-NV for linux-arm-kernel@lists.infradead.org; Tue, 19 Jan 2021 20:37:18 +0000 X-Originating-IP: 86.202.109.140 Received: from localhost (lfbn-lyo-1-13-140.w86-202.abo.wanadoo.fr [86.202.109.140]) (Authenticated sender: alexandre.belloni@bootlin.com) by relay6-d.mail.gandi.net (Postfix) with ESMTPSA id 7A695C0006; Tue, 19 Jan 2021 20:37:10 +0000 (UTC) Date: Tue, 19 Jan 2021 21:37:10 +0100 From: Alexandre Belloni To: Steen Hegelund Subject: Re: [PATCH v3 2/3] reset: mchp: sparx5: add switch reset driver Message-ID: <20210119203710.GP3666@piout.net> References: <20210114162432.3039657-1-steen.hegelund@microchip.com> <20210114162432.3039657-3-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210114162432.3039657-3-steen.hegelund@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210119_153717_956014_050E10A6 X-CRM114-Status: GOOD ( 24.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Gregory Clement , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Philipp Zabel , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This commit is also missing a commit message and you could probably get some info from your cover letter here. On 14/01/2021 17:24:31+0100, Steen Hegelund wrote: > Signed-off-by: Steen Hegelund > --- > drivers/reset/Kconfig | 8 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-microchip-sparx5.c | 120 +++++++++++++++++++++++++ > 3 files changed, 129 insertions(+) > create mode 100644 drivers/reset/reset-microchip-sparx5.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 71ab75a46491..05c240c47a8a 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -101,6 +101,14 @@ config RESET_LPC18XX > help > This enables the reset controller driver for NXP LPC18xx/43xx SoCs. > > +config RESET_MCHP_SPARX5 > + bool "Microchip Sparx5 reset driver" > + depends on HAS_IOMEM || COMPILE_TEST > + default y if SPARX5_SWITCH > + select MFD_SYSCON > + help > + This driver supports switch core reset for the Microchip Sparx5 SoC. > + > config RESET_MESON > tristate "Meson Reset Driver" > depends on ARCH_MESON || COMPILE_TEST > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 1054123fd187..341fd9ab4bf6 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o > obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o > obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o > obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o > +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o > obj-$(CONFIG_RESET_MESON) += reset-meson.o > obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o > obj-$(CONFIG_RESET_NPCM) += reset-npcm.o > diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c > new file mode 100644 > index 000000000000..0dbd2b6161ef > --- /dev/null > +++ b/drivers/reset/reset-microchip-sparx5.c > @@ -0,0 +1,120 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* Microchip Sparx5 Switch Reset driver > + * > + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. > + * > + * The Sparx5 Chip Register Model can be browsed at this location: > + * https://github.com/microchip-ung/sparx-5_reginfo > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PROTECT_REG 0x84 > +#define PROTECT_BIT BIT(10) > +#define SOFT_RESET_REG 0x08 > +#define SOFT_RESET_BIT BIT(1) > + > +struct mchp_reset_context { > + struct regmap *cpu_ctrl; > + struct regmap *gcb_ctrl; > + struct reset_controller_dev rcdev; > +}; > + > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct mchp_reset_context *ctx = > + container_of(rcdev, struct mchp_reset_context, rcdev); > + u32 val; > + I would ensure the reset only happens once here else I'm not sure how you could do it from the individual drivers. > + /* Make sure the core is PROTECTED from reset */ > + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); > + > + /* Start soft reset */ > + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); > + > + /* Wait for soft reset done */ > + return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, > + (val & SOFT_RESET_BIT) == 0, > + 1, 100); > +} > + -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel