From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3DD9C433DB for ; Fri, 22 Jan 2021 15:22:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A37A823A84 for ; Fri, 22 Jan 2021 15:22:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A37A823A84 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Owner; bh=20LwQOShfQmN9Vx3V3y3EhPkB07l3vvVDtz+slVs3Ac=; b=EhMPVExcWPB5+9p6x9d3hjsXa4 KVElBXCdKMzVLna2R0Qo9mS6mgDb/w0FrGPQpOtogX5U3Ta7iWMLETVJPrHiOuxNJxghJ0PtWr5XA o3E/WSNPu5bYLMFHWJsryDW34jimYUVMxWI3lpHYYuS/5tcC3yOhckm+CTggT9bSZJmbxY1F6fvCq xv9plvsADN/FPVOmYe3wRtZmZEligH1qIi1E80RbyEf5ZxsYVkTX6xQljiCqCj1bzXjtbwhAvzMLn zPJpQfYEfp6pkH4hOEUo3Q996qFcCMrcnvY8BCvtu55yoMeU+VZCOAfr8sPw9lo+nyVTYt3xD4bCO 7CIWLH5Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2yEm-0000ot-MH; Fri, 22 Jan 2021 15:20:37 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2yEi-0000l8-2P for linux-arm-kernel@lists.infradead.org; Fri, 22 Jan 2021 15:20:33 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 855A0235DD; Fri, 22 Jan 2021 15:20:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611328830; bh=NM97JC9VUtDaoZ/0hery6nL0ZqgOjpFiDdsyG8H34pE=; h=From:To:Cc:Subject:Date:From; b=PWGWMmQtCJR9xolMwCjFj2txaSH76OzfygdIH58bMR0SEJfMMHayFJ5hVimKsfVrs 2AMj7LbH+xen5C+HFohxnPHvsbZM90BEsdrKN9HBlQtGhvCv2f94dxtaMw/EvQv83+ s3EABeKDMOessGcCWvxWX/sF7DWQPeKLZCvUHpo8k5xf2IVg/meU7s741zvjRzcwWc I4lac5S5RD2c/int2eMw/js/LClhmKxemvZqNglhJ4AEqFmqZ/mYgUhna5x35ld6KQ 2svmcp18eHVobPSD+fNq9bFoveBc44pRsxL09YXV28T6pWFSVq+/VVFvBqt+BFrLuV W/tFKYT+nyAvw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: decompressor: cover BSS in cache clean and reorder with MMU disable on v7 Date: Fri, 22 Jan 2021 16:20:12 +0100 Message-Id: <20210122152012.30075-1-ardb@kernel.org> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_102032_213483_FBEB3DB3 X-CRM114-Status: GOOD ( 13.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maz@kernel.org, linux@armlinux.org.uk, Ard Biesheuvel MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To ensure that no cache lines cover any of the data that is accessed by the booting kernel with the MMU off, cover the uncompressed kernel's BSS region in the cache clean operation. Also, to ensure that no cachelines are allocated while the cache is being cleaned, perform the cache clean operation *after* disabling the MMU and caches when running on v7 or later, by making a tail call to the clean routine from the cache_off routine. This requires passing the VA range to cache_off(), which means some care needs to be taken to preserve R0 and R1 across the call to cache_off(). Since this makes the first cache clean redundant, call it with the range reduced to zero. This only affects v7, as all other versions ignore R0/R1 entirely. Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/head.S | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index caa27322a0ab..b0e5c41cefc5 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -614,11 +614,24 @@ not_relocated: mov r0, #0 mov r3, r7 bl decompress_kernel + @ + @ Perform a cache clean before disabling the MMU entirely. + @ In cases where the MMU needs to be disabled first (v7+), + @ the clean is performed again by cache_off(), using by-VA + @ operations on the range [R0, R1], making this prior call to + @ cache_clean_flush() redundant. In other cases, the clean is + @ performed by set/way and R0/R1 are ignored. + @ + mov r0, #0 + mov r1, #0 + bl cache_clean_flush + get_inflated_image_size r1, r2, r3 + ldr r2, =_kernel_bss_size + add r1, r1, r2 - mov r0, r4 @ start of inflated image - add r1, r1, r0 @ end of inflated image - bl cache_clean_flush + mov r0, r4 @ start of decompressed kernel + add r1, r1, r0 @ end of kernel BSS bl cache_off #ifdef CONFIG_ARM_VIRT_EXT @@ -1135,12 +1148,14 @@ proc_types: * reading the control register, but ARMv4 does. * * On exit, - * r0, r1, r2, r3, r9, r12 corrupted + * r0, r1, r2, r3, r9, r10, r11, r12 corrupted * This routine must preserve: * r4, r7, r8 */ .align 5 cache_off: mov r3, #12 @ cache_off function + mov r10, r0 + mov r11, r1 b call_cache_fn __armv4_mpu_cache_off: @@ -1187,7 +1202,9 @@ __armv7_mmu_cache_off: mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB - mov pc, lr + + mov r0, r10 + b __armv7_mmu_cache_flush /* * Clean and flush the cache to maintain consistency. -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel