From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF821C433E0 for ; Wed, 3 Feb 2021 13:24:41 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D63364DC4 for ; Wed, 3 Feb 2021 13:24:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D63364DC4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=01aThDAqCsoEH2xFGBXNg3oN9UWuUshcoXWQjMr47s8=; b=PT4DaZe47Xo4mzE+VfmY+aiB7 wCAic0Ner8GBMjciJqjiAhDdJsDpH+4xGxbihBa9d8MjSLcXLZxPcX967yZn8uhMZepveW7ZlzOxq 7Q1c6jNkaJLalMRDgB5ghTC2urCwHiNcZENCAadYC1wVrcKgtFkhCmKW+sa8JM2opVwNRsuF6kNzK kk+bIt9pUjVNXPfdmpqcT3y1WBt4VgmjqyhemiruK0seZeVyJ/0cnJMe6kyTjm/ZmaVGOzRlG0ce8 pQWN0qnaE7ojQnp3O1llnaQGj/H7OH77O59HDVgWSKLjHD47KMuJQx7mUmj+9AG3Mn1nXNFrkHtJx siX+5xwVQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7I87-0001UW-Q4; Wed, 03 Feb 2021 13:23:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7I85-0001Tz-Dd for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 13:23:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C884D6E; Wed, 3 Feb 2021 05:23:29 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.11.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CD213F73B; Wed, 3 Feb 2021 05:23:27 -0800 (PST) Date: Wed, 3 Feb 2021 13:23:24 +0000 From: Mark Rutland To: Shaokun Zhang Subject: Re: [PATCH v2 5/8] drivers/perf: hisi: Update DDRC PMU for programable counter Message-ID: <20210203132324.GK55896@C02TD0UTHF1T.local> References: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> <1612338668-40493-6-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1612338668-40493-6-git-send-email-zhangshaokun@hisilicon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_082333_728940_9A27141F X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qi Liu , John Garry , Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Cameron Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 03, 2021 at 03:51:05PM +0800, Shaokun Zhang wrote: > DDRC PMU's events are useful for performance profiling, but the events > are limited and counters are fixed. On HiSilicon Hip09 platform, PMU > counters are the programmable and more events are supported. Let's > add the DDRC PMU v2 driver. > static struct attribute *hisi_ddrc_pmu_v1_events_attr[] = { > HISI_PMU_EVENT_ATTR(flux_wr, 0x00), > HISI_PMU_EVENT_ATTR(flux_rd, 0x01), > @@ -240,6 +370,18 @@ static const struct attribute_group hisi_ddrc_pmu_v1_events_group = { > .attrs = hisi_ddrc_pmu_v1_events_attr, > }; > > +static struct attribute *hisi_ddrc_pmu_v2_events_attr[] = { > + HISI_PMU_EVENT_ATTR(clocks, 0x00), Should that be 'cycles' ? > + HISI_PMU_EVENT_ATTR(flux_wr, 0x83), > + HISI_PMU_EVENT_ATTR(flux_rd, 0x84), > + NULL > +}; The commit message mentioned that v2 supports more events, but this only adds three of them (and v2 listed eight distinct events). Is there a rationale for only listing these events specifically? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel