From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B67E2C433E0 for ; Wed, 3 Feb 2021 13:30:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C378864F55 for ; Wed, 3 Feb 2021 13:30:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C378864F55 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wbOqKl7tFJ/u31zq1VHobBONwt3Fe0yQK5Q1+5G9h5Q=; b=DAAHnJAIfUSY08GBQD/nNnKS+ tEaoAE1XWGtjKgUdxCUdEgm2mUBTcpnSkrSFbBxmofC3iuhfRQByAAygrVgovZS4xvIsm8AxMuigU zhxaMPknAiRjacA/Ver9oxloXlwe+qxCvRxI1U8Od/xSCucjMtUVZXTuBGsHCTw5r147h31pKEjXX Akmqup6zTJA/JOy7yfDTjO7OfxXxxYCXNMNM1O9hGRMGtGCvJH3wiBT0w47BBTVST84bwFOW5hUBJ Po1upi7z8vBknHo6bK3lt0vBfVRJkD19S1mM7yLSNaXDAcHuIW3Zzg4dfve9LztqJ3O7XE+9O9VLW akg/vDOvw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7IDT-0002NS-E2; Wed, 03 Feb 2021 13:29:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7IDR-0002Mo-NV for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 13:29:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 23776D6E; Wed, 3 Feb 2021 05:29:03 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.11.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8FA253F73B; Wed, 3 Feb 2021 05:29:01 -0800 (PST) Date: Wed, 3 Feb 2021 13:28:58 +0000 From: Mark Rutland To: Shaokun Zhang Subject: Re: [PATCH v2 6/8] drivers/perf: hisi: Add support for HiSilicon SLLC PMU driver Message-ID: <20210203132858.GL55896@C02TD0UTHF1T.local> References: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> <1612338668-40493-7-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1612338668-40493-7-git-send-email-zhangshaokun@hisilicon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_082905_864731_0880251A X-CRM114-Status: GOOD ( 12.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qi Liu , John Garry , Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Cameron Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 03, 2021 at 03:51:06PM +0800, Shaokun Zhang wrote: > HiSilicon's Hip09 is comprised by multi-dies that can be connected by SLLC > module (Skyros Link Layer Controller), its has separate PMU registers which > the driver can program it freely and interrupt is supported to handle > counter overflow. Let's support its driver under the framework of HiSilicon > uncore PMU driver. [...] > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_lo, config1, 10, 0); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_hi, config1, 21, 11); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44); If you could describe these fields in the commit message that would be helpful. What is a 'tgtid'? Is that a 'target ID' or something to that effect? [...] > + HISI_PMU_FORMAT_ATTR(tgtid_low, "config1:0-10"), > + HISI_PMU_FORMAT_ATTR(tgtid_high, "config1:11-21"), Does this need to be exposed to userspace in two halves, rather than being a single 'tgtid' field that the driver can decompose as necessary? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel