From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2400C433E0 for ; Mon, 8 Feb 2021 22:51:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56C3F64DA1 for ; Mon, 8 Feb 2021 22:51:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 56C3F64DA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hdYByW3Wb5PQBabOhOe0zSeki4DkwZb6mk1qDySO8BI=; b=YJSFRFUnghkspQeHC8bc2y9Jx Rh3yFeGNtDKoexsRooEt1aqVYku9B9XS23asyA6XbDd5qoQH60Jb1hW1+AX72+oYfeYT2O95kFrDj n7PYL0nBbeTVEWYZlCULXVMpImrb4EzScbJdr5p+Qy6/2UbDNAJIE8Rbiylo2pp9dlcsmYuDA8lWz 6ykA2l/73mKYHM9b9r4/zQZzse/eT+KpLVMSHNaQlaGDhNh3JJX3fVtLUpKxQqdsv0hC44CglkeZy PvUvyQY+BeNz0ME7viz50nx3sk2Z2GRlAnOap4oFqnb4K3fNn05rVYdNLX8Dvk/2JsSl4QZs0/E9M 1zNyEx5lQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9FMM-0007CH-Ng; Mon, 08 Feb 2021 22:50:22 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9FMG-0007Ax-IU for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 22:50:18 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6317564E7A; Mon, 8 Feb 2021 22:50:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612824615; bh=SmL5d665DCFErAiZfmaaEzfyRA/Q0MiXWS5YIX/3lgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s5wDrrXHHWFxbVfvV/xAghENV8/EHqcbOXLJM54PZi+e6fU9pjJLB0IgIWll3p6oI BobIoBEnH5MqutX4i4R7JKKtjnIeGmaWnirj8ZuW4yuIbsLV1MTcYls0ce3GibQ1JR Mibmt2ysj8UHOvT+jGe5tJt2PUEc1vh7Vl2IcL99DFaNM/xsuYCrZj+I5++2qvwIrn 1rQdT1R2tEWErdRtrDZNc2LcrcId7U/f0p+ZEEkOAzT32JvdZ7QqU9ln9ZtoQSa8cT S332/YZqHXA55GgCwdEB6RMTlH2JdSHuIlJweCnTaPj9bh0g0gR3/FBhq6FjKnJki4 aSDyxk23PgkJw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] ARM: cache-v7: get rid of mini-stack Date: Mon, 8 Feb 2021 23:49:59 +0100 Message-Id: <20210208224959.13683-4-ardb@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210208224959.13683-1-ardb@kernel.org> References: <20210208224959.13683-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_175016_829883_853895F9 X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have reduced the number of registers that we need to preserve when calling v7_invalidate_l1 from the boot code, we can use scratch registers to preserve the remaining ones, and get rid of the mini stack entirely. This works around any issues regarding cache behavior in relation to the uncached accesses to this memory, which is hard to get right in the general case (i.e., both bare metal and under virtualization) While at it, switch v7_invalidate_l1 to using ip as a scratch register instead of r4. This makes the function AAPCS compliant, and removes the need to stash r4 in ip across the call. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 15 -------- arch/arm/mm/cache-v7.S | 10 ++--- arch/arm/mm/proc-v7.S | 40 +++++++++----------- 3 files changed, 23 insertions(+), 42 deletions(-) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 2f841cb65c30..a711322d9f40 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -150,21 +150,6 @@ extern unsigned long vectors_base; */ #define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET) -#ifdef CONFIG_XIP_KERNEL -/* - * When referencing data in RAM from the XIP region in a relative manner - * with the MMU off, we need the relative offset between the two physical - * addresses. The macro below achieves this, which is: - * __pa(v_data) - __xip_pa(v_text) - */ -#define PHYS_RELATIVE(v_data, v_text) \ - (((v_data) - PAGE_OFFSET + PLAT_PHYS_OFFSET) - \ - ((v_text) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) + \ - CONFIG_XIP_PHYS_ADDR)) -#else -#define PHYS_RELATIVE(v_data, v_text) ((v_data) - (v_text)) -#endif - #ifndef __ASSEMBLY__ /* diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 4544af4855f6..243e82124663 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -53,12 +53,12 @@ ENTRY(v7_invalidate_l1) and r2, r0, #0x7 add r2, r2, #4 @ SetShift -1: movw r4, #0x7fff - and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] +1: movw ip, #0x7fff + and r0, ip, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] -2: mov r4, r0, lsl r2 @ NumSet << SetShift - orr r4, r4, r3 @ Reg = (Temp<