Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks

Mathieu Poirier
2021-02-16T20:32:10Z

On Mon, Feb 15, 2021 at 05:58:37PM +0000, Mike Leach wrote:
> Hi Mathieu,
>
> On Mon, 15 Feb 2021 at 16:56, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
> >
> > On Mon, Feb 15, 2021 at 04:27:26PM +0000, Mike Leach wrote:
> > > HI Anshuman
> > >
> > > On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
> > > <anshuman.khandual@arm.com> wrote:
> > > >
> > > > Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> > > > TRBE). To allow quicker access to the sink for a given CPU bound source,
> > > > keep a percpu array of the sink devices. Also, add support for building
> > > > a path to the CPU local sink from the ETM.
> > > >
> > >
> > > Really need to tighten up the terminology here - I think what you mean
> > > is a PE architecturally defined sink - i.e. one that can be determined
> > > by reading the feature registers on the PE, rather than an ETR which
> > > cannot.
> > > However, the Coresight Base System Architecture specification does
> > > recommend a per cpu design using an ETR per CPU - now I assume that
> > > this case is not catered for in this patch?
> > >
> > > > This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> > > > This new sink type is exclusively available and can only work with percpu
> > > > source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> > > >
> > >
> > > CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist.
> > >
> > > >
> > > > This defines a percpu structure that accommodates a single coresight_device
> > > > which can be used to store an initialized instance from a sink driver. As
> > > > these sinks are exclusively linked and dependent on corresponding percpu
> > > > sources devices, they should also be the default sink device during a perf
> > > > session.
> > > >
> > > > Outwards device connections are scanned while establishing paths between a
> > > > source and a sink device. But such connections are not present for certain
> > > > percpu source and sink devices which are exclusively linked and dependent.
> > > > Build the path directly and skip connection scanning for such devices.
> > > >
> > > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > > Cc: Mike Leach <mike.leach@linaro.org>
> > > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > > ---
> > > > Changes in V3:
> > > >
> > > > - Updated coresight_find_default_sink()
> > > >
> > > > drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
> > > > include/linux/coresight.h | 12 ++++++++++++
> > > > 2 files changed, 26 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> > > > index 0062c89..4795e28 100644
> > > > --- a/drivers/hwtracing/coresight/coresight-core.c
> > > > +++ b/drivers/hwtracing/coresight/coresight-core.c
> > > > @@ -23,6 +23,7 @@
> > > > #include "coresight-priv.h"
> > > >
> > > > static DEFINE_MUTEX(coresight_mutex);
> > > > +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
> > > >
> > >
> > > If you do indeed mean the architecturally defined sinks then this
> > > could be 'csdev_pe_arch_sink' - or something similar to indicate the
> > > reliance on the PE architecture, unless per-cpu ETR topologies are
> > > also handled here.
> >
> > I would like to treat systems with one ETR per CPU the same way we do for TRBEs.
> > That way we have two distinct way of working, i.e topologies where the sink is
> > shared and 1:1 topologies. As such moving forward with "csdev_pe_arch_sink"
> > could become misleading when 1:1 ETR topologies are supported.
> >
> > Mathieu
> >
>
> I believe that In terms of connecting source -> sink for 1:1 ETM:ETR,
> then the existing code will already work via the normal build path and
> ports declarations. Suzukis changes in coresight-etm-perf to allow
> multiple sinks of the same type to be active for ETE:TRBE will also
> work for ETx:ETR. (at least in terms of path building - there may
> still be other issues that come into play about buffers etc).
>
> The TRBE .dts doesn''t have any ports and is as such outside this
> framework. This patch appears to be making it detectable when
> connecting source -> sink where we have ETE:TRBE on a given CPU - as
> in the subsequent patches, the TRBE driver registers in the per cpu
> sink array.
>
> So these changes are not really related to 1:1 specifically, but the
> detectability of PE architected sinks. There is a need for the per cpu
> array for TRBE as there is no other way of finding them - but not for
> ETR - which should work just fine without changes I think.

I thought about this further after reading the above... ETRs have ports, they
are present in the DTS and are already supported. There is no point in trying
to handle them the same way TRBEs are handled in this set. We can look at the
(potential) advantage of doing so at a later time if the need arises but not in
this set.

Thanks,
Mathieu

>
> Regards
>
> Mike
>
>
> > >
> > > > /**
> > > > * struct coresight_node - elements of a path, from source to sink
> > > > @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
> > > > if (csdev == sink)
> > > > goto out;
> > > >
> > > > + if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> > > > + sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> > > > + _coresight_build_path(sink, sink, path);
> > > > + found = true;
> > > > + goto out;
> > > > + }
> > > > +
> > > > /* Not a sink - recursively explore each port found on this element */
> > > > for (i = 0; i < csdev->pdata->nr_outport; i++) {
> > > > struct coresight_device *child_dev;
> > > > @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
> > > > int depth = 0;
> > > >
> > > > /* look for a default sink if we have not found for this device */
> > > > - if (!csdev->def_sink)
> > > > - csdev->def_sink = coresight_find_sink(csdev, &depth);
> > > > + if (!csdev->def_sink) {
> > > > + if (coresight_is_percpu_source(csdev))
> > > > + csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> > > > + if (!csdev->def_sink)
> > > > + csdev->def_sink = coresight_find_sink(csdev, &depth);
> > > > + }
> > > > return csdev->def_sink;
> > > > }
> > > >
> > > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> > > > index 976ec26..bc3a5ca 100644
> > > > --- a/include/linux/coresight.h
> > > > +++ b/include/linux/coresight.h
> > > > @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
> > > > CORESIGHT_DEV_SUBTYPE_SINK_PORT,
> > > > CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
> > > > CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> > > > + CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
> > >
> > > If this is needed then could it not be ..._SINK_SYSMEM_PROC - to be
> > > consistent with ..._SOURCE_PROC?
> > >
> > > > };
> > > >
> > > > enum coresight_dev_subtype_link {
> > > > @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
> > > > csa->write(val, offset, false, true);
> > > > }
> > > >
> > > > +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
> > >
> > > All cpu sources are per cpu - that is ETMv3, ETMv4, PTM, ETE - this
> > > might be better as simply coresight_is_cpu_source() as all the
> > > aforementioned types will return true.
> > >
> > > > +{
> > > > + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> > > > + csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
> > > > +}
> > > > +
> > > > +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> > > > +{
> > > > + return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> > > > + csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> > > > +}
> > > > #else /* !CONFIG_64BIT */
> > > >
> > > > static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> > > > --
> > > > 2.7.4
> > > >
> > >
> > > Regards
> > >
> > > Mike
> > > --
> > > Mike Leach
> > > Principal Engineer, ARM Ltd.
> > > Manchester Design Centre. UK
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK