Re: [PATCH V3 09/14] arm64: Add TRBE definitions

Suzuki K Poulose
2021-01-28T09:32:57Z

On 1/27/21 8:55 AM, Anshuman Khandual wrote:
> This adds TRBE related registers and corresponding feature macros.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>

> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

> ---
> Changes in V3:
>
> - ID_AA64DFR0_TRBE_SHIFT has been moved here from the TRBE driver
> - Changed TRBLIMITR_TRIG_MODE_SHIFT as 3
>
> arch/arm64/include/asm/sysreg.h | 50 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 4acff97..85ae4db 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -329,6 +329,55 @@
>
> /*** End of Statistical Profiling Extension ***/
>
> +/*
> + * TRBE Registers
> + */
> +#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
> +#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
> +#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
> +#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
> +#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
> +#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
> +#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
> +
> +#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
> +#define TRBLIMITR_LIMIT_SHIFT 12
> +#define TRBLIMITR_NVM BIT(5)
> +#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
> +#define TRBLIMITR_TRIG_MODE_SHIFT 3
> +#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
> +#define TRBLIMITR_FILL_MODE_SHIFT 1
> +#define TRBLIMITR_ENABLE BIT(0)
> +#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
> +#define TRBPTR_PTR_SHIFT 0
> +#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
> +#define TRBBASER_BASE_SHIFT 12
> +#define TRBSR_EC_MASK GENMASK(5, 0)
> +#define TRBSR_EC_SHIFT 26
> +#define TRBSR_IRQ BIT(22)
> +#define TRBSR_TRG BIT(21)
> +#define TRBSR_WRAP BIT(20)
> +#define TRBSR_ABORT BIT(18)
> +#define TRBSR_STOP BIT(17)
> +#define TRBSR_MSS_MASK GENMASK(15, 0)
> +#define TRBSR_MSS_SHIFT 0
> +#define TRBSR_BSC_MASK GENMASK(5, 0)
> +#define TRBSR_BSC_SHIFT 0
> +#define TRBSR_FSC_MASK GENMASK(5, 0)
> +#define TRBSR_FSC_SHIFT 0
> +#define TRBMAR_SHARE_MASK GENMASK(1, 0)
> +#define TRBMAR_SHARE_SHIFT 8
> +#define TRBMAR_OUTER_MASK GENMASK(3, 0)
> +#define TRBMAR_OUTER_SHIFT 4
> +#define TRBMAR_INNER_MASK GENMASK(3, 0)
> +#define TRBMAR_INNER_SHIFT 0
> +#define TRBTRG_TRG_MASK GENMASK(31, 0)
> +#define TRBTRG_TRG_SHIFT 0
> +#define TRBIDR_FLAG BIT(5)
> +#define TRBIDR_PROG BIT(4)
> +#define TRBIDR_ALIGN_MASK GENMASK(3, 0)
> +#define TRBIDR_ALIGN_SHIFT 0
> +
> #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
> #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
>
> @@ -831,6 +880,7 @@
> #define ID_AA64MMFR2_CNP_SHIFT 0
>
> /* id_aa64dfr0 */
> +#define ID_AA64DFR0_TRBE_SHIFT 44
> #define ID_AA64DFR0_TRACE_FILT_SHIFT 40
> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
> #define ID_AA64DFR0_PMSVER_SHIFT 32