From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78136C433DB for ; Wed, 17 Feb 2021 11:28:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A4F464D92 for ; Wed, 17 Feb 2021 11:28:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A4F464D92 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eyYO/boFFq604O0d7OIAiR3ittD2awWZcR0HUsS6zoU=; b=Shvk7+2bmQKokp9XowLCmBbHU eDSyNnq9aBabiD8HeQ1P8eD2D8CDAzvJ28RrkDiMuE/2lUCVbUksVIldkrmZTp8BslN8iXnlMd60B GNHB9vguCxf2YjsD0B/WSlaqeCJoz9cWapqYPCNuXThItDOxwfUkcLojgrbbQkPAuLofdq4RzZiUx vlpXZmChmSl8I2aFtukVrEzUCE5c5TyBGk1y0eVoKXqw5fmCCgMxyfhEZJijl5WE683ZJZJh+QGdI 34gFtCxwUyAlVixUvYhbRpaj70TY5rhHs/+r+3IYQI0FNyn3snwmrzzX0XpeDUytaTtRhbDtlJPEn qnhq7XQiQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lCKxN-0002Ot-7E; Wed, 17 Feb 2021 11:25:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lCKxJ-0002O0-VZ for linux-arm-kernel@lists.infradead.org; Wed, 17 Feb 2021 11:25:18 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4023964DBD; Wed, 17 Feb 2021 11:25:15 +0000 (UTC) Date: Wed, 17 Feb 2021 11:25:12 +0000 From: Catalin Marinas To: Rich Wiley Subject: Re: [PATCH] arm64: kernel: disable CNP on Carmel Message-ID: <20210217112512.GE17184@arm.com> References: <20210217013151.30351-1-rwiley@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210217013151.30351-1-rwiley@nvidia.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210217_062518_102605_742E76F1 X-CRM114-Status: GOOD ( 20.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 16, 2021 at 05:31:51PM -0800, Rich Wiley wrote: > On NVIDIA Carmel cores, CNP behaves differently than it does on standard > ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB > entry created by core0 for a specific ASID, a non-shareable TLBI from > core1 may still see the shared entry. On standard ARM cores, that TLBI > will invalidate the shared entry as well. > > This causes issues with patchsets that attempt to do local TLBIs based > on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling > CNP support for NVIDIA Carmel cores. > > Signed-off-by: Rich Wiley > --- > arch/arm64/kernel/cpufeature.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9fac745aa7bb..2aa38a430f6a 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -986,6 +986,12 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, > return ctr & BIT(CTR_DIC_SHIFT); > } > > +static bool cpu_has_broken_cnp(void) > +{ > + const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL); > + return is_midr_in_range(read_cpuid_id(), &range); > +} Since this is a CPU erratum, can you please implement it as other errata workarounds we have in the kernel? You'd need to provide an erratum number for this CPU as well. You could make the .capability definition of the erratum entry more generic like ARM64_WORKAROUND_BROKEN_CNP. Thanks. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel