From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A47C433E0 for ; Thu, 18 Feb 2021 14:24:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3DD664E85 for ; Thu, 18 Feb 2021 14:24:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B3DD664E85 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9ot1GA6QQYVxTI8N38KCBSU0QuLWuvRgmNOudyQUeaM=; b=pnR+rydACr6W+vwCcmU7W2cjJ DsfjlZQ2vjx63EOcJkeA62koqnknjpOoKFHbNmE4f2p/+Bfppz37RVnScCN3rTfODNpJyWOU3IQrs GY0uclkYpBoQQ1XFgZrnBuOUXE9cSVZZnPWkOPORKI7l91MKElyV4SnWmAXxQWKA5kwYLUm+IIXx/ s3jlrXCSGhYBuzkSSBTmtyt7shKKgbokU8Ofr2vKUoNQJW9d+wO5rHgylrTFsUendOzfAoG1r4hXu oXSzE5PidJrBYgYWbbDCvWFv9BcW2AxORz0QmvJ6Ph+SFHiuqZDN1Cf/g5VINlAyWoxXx24sfdjDV Fra+JeRAg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lCkC8-0006Rc-IR; Thu, 18 Feb 2021 14:22:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lCkC6-0006R2-7G for linux-arm-kernel@lists.infradead.org; Thu, 18 Feb 2021 14:22:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 28640ED1; Thu, 18 Feb 2021 06:22:12 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.48.237]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AE8663F73B; Thu, 18 Feb 2021 06:22:08 -0800 (PST) Date: Thu, 18 Feb 2021 14:22:05 +0000 From: Mark Rutland To: Hector Martin Subject: Re: [PATCH v2 08/25] arm64: Always keep DAIF.[IF] in sync Message-ID: <20210218142205.GB89209@C02TD0UTHF1T.local> References: <20210215121713.57687-1-marcan@marcan.st> <20210215121713.57687-9-marcan@marcan.st> <20210217122200.GC5556@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210218_092214_409317_4ED6DDED X-CRM114-Status: GOOD ( 32.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnd Bergmann , Rob Herring , Tony Lindgren , Marc Zyngier , Linus Walleij , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Alexander Graf , Olof Johansson , Mohamed Mediouni , Mark Kettenis , Will Deacon , linux-arm-kernel@lists.infradead.org, Stan Skowronek Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 18, 2021 at 09:51:40PM +0900, Hector Martin wrote: > On 17/02/2021 21.22, Mark Rutland wrote: > > > Root irqchip drivers can discriminate between IRQs and FIQs by checking > > > the ISR_EL1 system register. > > > > I think we can remove this note for now. If we go with seperate handlers > > this won't be necessary, and if not this would be better placed on a > > commit adding the FIQ handling capability. > > Indeed, this doesn't make sense any more. Changed for v3. > > > Judging by `git grep -Wi daif -- arch/arm64`, with this patch applied, > > we'll also need fixups in: > > > > * gic_arch_enable_irqs() in arch/arm64/include/asm/arch_gicv3.h > > * save_and_disable_irq() in arch/arm64/include/asm/assembler.h (noted below) > > * local_daif_save_flags() in arch/arm64/include/asm/daifflags.h > > (the fake DAIF should have F set too) > > * __cpu_do_idle_irqprio() in arch/arm64/kernel/process.c > > Good catches. A few of those are irrelevant for M1 but need to be done now > that we're making this change globally, others I just missed from the > beginning. Sure; my general view is that we should aim for consistency, and should ensure that DAIF.F==DAIF.I at all times on all platforms unless we have a strong reason to violate that rule. That generally makes it easier to reason about the code and avoid accidentally breaking M1/non-M1 if/when we refactor masking logic. > There's also an incorrect comment in entry.S: > > /* > * DA_F were cleared at start of handling. If anything is set in > * DAIF, we come back from an NMI, so skip preemption > */ > mrs x0, daif > orr x24, x24, x0 > > Now only DA__ are cleared. This actually pairs with gic_arch_enable_irqs() > and begs the question: in priority masking systems, do we unmask both IRQ > and FIQ (the gic_arch_enable_irqs change), or do we leave FIQ masked (which > instead would need an AND in that part of entry.S so as to not consider FIQ > masked as meaning we're coming back from an NMI)? I think that for consistency we always want to keep IRQ and FIQ in-sync, even when using GIC priorities. So when handling a pseudo-NMI we should unmask DAIF.DA and leave DAIF.IF masked. > And a minor related one: should init_gic_priority_masking() WARN if FIQ is > masked too? This probably goes with the above. I think it should, yes. > Either way, this was nontrivial to make sense of, so I'll make that entry.S > comment clearer while I'm touching it. Sounds good; thanks! > > I think save_and_diable_irq below needs to be updated too, since it > > only sets DAIF.I and leaves DAIF.F as-is. > > Totally missed this one! Fixed for v3. > > > > - * FIQ is never expected, but we mask it when we disable debug exceptions, and > > > - * unmask it at all other times. > > > + * FIQ is never expected on most platforms, but we keep it synchronized > > > + * with the IRQ mask status. On platforms that do not expect FIQ, that vector > > > + * triggers a kernel panic. On platforms that do, the FIQ vector is unified > > > + * with the IRQ vector. > > > */ > > > > Can we please delete this bit, though? Now that we say IRQ and FIQ are > > masked/unmasked together, I don't think the rest is necessary to > > understand the masking logic, and it's one less thing to keep in sync > > with changes to the entry code. > > Gone :) Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel