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spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TgcYMlEs2a3HfogttarLztaEwmfNCwifvjARi7vBuJk=; b=Bq+Q0obLStidxOhGOQ+51LYEq TdYEBjQTmhCxjCWwnsA+U1gzIrdQsD+mAMi80yx/O6+MN3yjfVzU98ab9aZFNjTCoE70xXfYdn5mc ZMswwhVfp/SxKwewyAxMWZ4Gfj+diPrLtS9TJDuEnYbw7YpSYNVbs85ZJY7+crhvjAXZhRSaYeUH9 8B9WQHprQKTJFOQ7t0oUIv6ylLVFfhTpvj04nt5GnWHMIyzgf7mI9x3kU2vh1vYCrux9AZSOA6LAv FjBL0JnHWB4lBL7XDq+eoZDJeyyVT1tFes2hU7enMsmIpTGxgE84x0YzEDERUnP8eR3El96tm/bdw /gi+as1Xg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lD9xB-0005v7-7r; Fri, 19 Feb 2021 17:52:33 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lD9x5-0005sm-KV for linux-arm-kernel@lists.infradead.org; Fri, 19 Feb 2021 17:52:29 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 99C2364ED9; Fri, 19 Feb 2021 17:52:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1613757146; bh=mn9kn5Bs6DUDViauax7d710EWCSTYspffhf6L+06LIg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fzJ+FvVBQdPVf1lj9RM113HrwU01U1xj2WtvxuSkI4qgGUg2Ivrgg9zoYHe5aOwGE /AXWl68s6fAYoZZAnH/3ZPxYleclaytuzBtAc9lf4q8Da1Fu9HnnxAH+ZdMCfM0+Xo iIBz8iepMfnUTRTiDQf6waJbc15RFxaz79CNUupt4d7t2cMc0m8CCD161pYPY/Xx3i LRLVR1ZFAhb4pRqnChY5RZC59L8eLdKwQ/Sh1Jr0oZIgE+8VXGT1a02DUb27ekyB9i eerllH9Bnk8SKM7/fk5EhrLXisY5A4++EC9I4AYM7GRNSy7ePRAVWF51oCl3da0ba7 ZMSTYn8NhuUsQ== Date: Fri, 19 Feb 2021 17:52:21 +0000 From: Will Deacon To: Neeraj Upadhyay Subject: Re: [PATCH] arm64: Add part number for Arm Cortex-A78 Message-ID: <20210219175220.GB6352@willie-the-truck> References: <1613580251-12694-1-git-send-email-neeraju@codeaurora.org> <20210217170612.GA4254@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210219_125227_795445_142ACCE0 X-CRM114-Status: GOOD ( 17.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, saiprakash.ranjan@codeaurora.org, catalin.marinas@arm.com, konrad.dybcio@somainline.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 17, 2021 at 11:37:04PM +0530, Neeraj Upadhyay wrote: > > > On 2/17/2021 10:36 PM, Will Deacon wrote: > > On Wed, Feb 17, 2021 at 10:14:11PM +0530, Neeraj Upadhyay wrote: > > > Add the MIDR part number info for the Arm Cortex-A78. > > > > > > Signed-off-by: Neeraj Upadhyay > > > --- > > > arch/arm64/include/asm/cputype.h | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > > > index ef5b040..3aced88 100644 > > > --- a/arch/arm64/include/asm/cputype.h > > > +++ b/arch/arm64/include/asm/cputype.h > > > @@ -72,6 +72,7 @@ > > > #define ARM_CPU_PART_CORTEX_A76 0xD0B > > > #define ARM_CPU_PART_NEOVERSE_N1 0xD0C > > > #define ARM_CPU_PART_CORTEX_A77 0xD0D > > > +#define ARM_CPU_PART_CORTEX_A78 0xD41 > > > #define APM_CPU_PART_POTENZA 0x000 > > > @@ -109,6 +110,7 @@ > > > #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) > > > #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) > > > #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) > > > +#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) > > > #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) > > > #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) > > > #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) > > > > This usually means there's an erratum to work around. What are you hiding ;) > > > > Will > > > > :) . This is needed for supporting implementation defined AMU counters in > A78 [1]. However, there is no upstream user of it. I don't think we should add this upstream without a user. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel