From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F197C433DB for ; Wed, 24 Feb 2021 14:08:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1BF964E90 for ; Wed, 24 Feb 2021 14:08:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A1BF964E90 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=d+Miw0XK0pjpmU87esI5Un23aNgM+MUfMsggUd18d64=; b=nXLi7PgVu5YUFw0fcG+Oa3ZVw zRr3nQ2QQ+oSjWVwHQQ5vZosVrmsUxpeCBciolTy1ZuyF47JoWcRl8397zfFN5tgLkzy5O3RuLLH9 +PeUDF2hU6m7gJa8piqdSETlYJZ85vV/ZondVe7pYHM6rDx0ANT4KzJB8J6ZrsCsmEOsd0bM2YhZC B8E/17e8BYUSde4vCF4lfoGas4S++eG9Dp2Lk/KX2vBpe2lwDXXcanXa4ifrMNICCggSJUuCM2X6Q Ml52XKJYAjIxXP3tUgeZ+lNtnn4UqwvGVDsrVqQv4Hl0+ll33mAiQh+9Qz0DhbBowQzLAZiNSgFAS TGgA/BEZA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lEuoq-0001dw-GJ; Wed, 24 Feb 2021 14:07:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lEuon-0001d7-1S for linux-arm-kernel@lists.infradead.org; Wed, 24 Feb 2021 14:07:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7962731B; Wed, 24 Feb 2021 06:07:01 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.52.137]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 642C43F70D; Wed, 24 Feb 2021 06:06:59 -0800 (PST) Date: Wed, 24 Feb 2021 14:06:56 +0000 From: Mark Rutland To: Marc Zyngier Subject: Re: [PATCH 0/8] arm64: Support FIQ controller registration Message-ID: <20210224140656.GG50741@C02TD0UTHF1T.local> References: <20210219113904.41736-1-mark.rutland@arm.com> <87a6s0orm7.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87a6s0orm7.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210224_090709_167228_43471856 X-CRM114-Status: GOOD ( 27.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, marcan@marcan.st, linux-kernel@vger.kernel.org, james.morse@arm.com, tglx@linutronix.de, will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Feb 19, 2021 at 06:10:56PM +0000, Marc Zyngier wrote: > Hi Mark, > > On Fri, 19 Feb 2021 11:38:56 +0000, > Mark Rutland wrote: > > > > Hector's M1 support series [1] shows that some platforms have critical > > interrupts wired to FIQ, and to support these platforms we need to support > > handling FIQ exceptions. Other contemporary platforms don't use FIQ (since e.g. > > this is usually routed to EL3), and as we never expect to take an FIQ, we have > > the FIQ vector cause a panic. > > > > Since the use of FIQ is a platform integration detail (which can differ across > > bare-metal and virtualized environments), we need be able to explicitly opt-in > > to handling FIQs while retaining the existing behaviour otherwise. This series > > adds a new set_handle_fiq() hook so that the FIQ controller can do so, and > > where no controller is registered the default handler will panic(). For > > consistency the set_handle_irq() code is made to do the same. > > > > The first couple of patches are from Marc's irq/drop-generic_irq_multi_handler > > branch [2] on kernel.org, and clean up CONFIG_GENERIC_IRQ_MULTI_HANDLER usage. > > The next four patches move arm64 over to a local set_handle_irq() > > implementation, which is written to share code with a set_handle_fiq() function > > in the last two patches. The only functional difference here is that if an IRQ > > is somehow taken prior to set_handle_irq() the default handler will directly > > panic() rather than the vector branching to NULL. > > > > The penultimate patch is cherry-picked from the v2 M1 series, and as per > > discussion there [3] will need a few additional fixups. I've included it for > > now as the DAIF.IF alignment is necessary for the FIQ exception handling added > > in the final patch. > > > > The final patch adds the low-level FIQ exception handling and registration > > mechanism atop the prior rework. > > Thanks for putting this together. I have an extra patch on top of this > series[1] that prevents the kernel from catching fire if a FIQ fires > whilst running a guest. Nothing urgent, we can queue it at a later time. > > Thanks, > > M. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/fiq IIUC for that "invalid_vect" should be changed to "valid_vect", to match the other valid vector entries, but otherwise that looks sane to me. I guess we could take that as a prerequisite ahead of the rest? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel