From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E250C433DB for ; Thu, 25 Feb 2021 18:34:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 16F2F64F27 for ; Thu, 25 Feb 2021 18:34:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 16F2F64F27 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7GyX49rKIfMP/mb9gtLF0aXzkbkkSniidLur6WTOM4Q=; b=sqU21X79uRPlWY23FnI/bTLf2 j7RggBUWquuY3cgWnrK3elUCsPrBBovwebZXo1nIMAn9WrTcKxsfwUqMzWJ2CSzbRB3eS8d4VsAUf feYQby095jZv/QnFc+qPx+EDzZR9YvME49BI6VGuXMs2TqVADbIDJdDxC3opWkjB9xofRhLt5pVFg nxbJyaOa216yujGAhavQuZ9qviTpdvkCavUpyOMKHx3ROSW1yaJYYGTZvUdyR6dm0a5+4cjPHAeoh NEz8/rGNJ6bqGliJ1QKGEgp87wSG7ub2bWETBi7uIEG+c+ymKrMJaoHHiJBXyQrpaLP5VjM1DT93/ v448025bw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lFLRp-0001jn-S3; Thu, 25 Feb 2021 18:33:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lFLRm-0001j3-IV for linux-arm-kernel@lists.infradead.org; Thu, 25 Feb 2021 18:33:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C961C1063; Thu, 25 Feb 2021 10:33:08 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.50.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5A88E3F73D; Thu, 25 Feb 2021 10:33:07 -0800 (PST) Date: Thu, 25 Feb 2021 18:33:04 +0000 From: Mark Rutland To: Alexandru Elisei Subject: Re: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world Message-ID: <20210225183304.GB41738@C02TD0UTHF1T.local> References: <1613042797-13109-1-git-send-email-anshuman.khandual@arm.com> <76566432-2f01-a0a6-26c6-1c2351a4c942@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <76566432-2f01-a0a6-26c6-1c2351a4c942@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210225_133310_683224_AE7F5FD1 X-CRM114-Status: GOOD ( 22.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andre.Przywara@arm.com, Suzuki.Poulose@arm.com, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, Anshuman Khandual Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Feb 12, 2021 at 05:33:08PM +0000, Alexandru Elisei wrote: > Hello, > > On 2/11/21 11:26 AM, Anshuman Khandual wrote: > > MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace > > buffer to use non-secure memory and to permit direct register accesses from > > the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and > > make sure TRBE is implemented. We still continue to reset MDCR_EL3 register > > to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB. > > > > Signed-off-by: Anshuman Khandual > > --- > > arch/aarch64/boot.S | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > > index 37f4b98..e47cf59 100644 > > --- a/arch/aarch64/boot.S > > +++ b/arch/aarch64/boot.S > > @@ -71,6 +71,14 @@ _start: > > ldr x1, =(0x3 << 12) > > orr x0, x0, x1 > > > > +1: mrs x1, id_aa64dfr0_el1 > > Nitpick: we could change the first read of ID_AA64DFR0_EL1 to use x2 as the > destination register, to avoid this second read. I've kept this as-is for now; my general preference is to keep things such that each of the feature enables can be read indepdendently, even if that requires some redundant work. > > + ubfx x1, x1, #44, #4 > > + cbz x1, 1f > > + > > + // Enable TRBE for the non-secure world. > > + ldr x1, =(0x3 << 24) > > + orr x0, x0, x1 > > + > > 1: msr mdcr_el3, x0 // Disable traps to EL3 > > Looked at [1] for the field definitions, and the patch indeed does what it says. > 0b11 for MDCR_EL3.NSTB means that the buffer owning regime is the non-secure > state, and accesses to the buffer control registers from the *secure state* are > trapped to EL3, which is what we want. > > With or without the destination register change: > > Reviewed-by: Alexandru Elisei Thanks for the review -- I folded your tag in. Mark. > > [1] https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ > > Thanks, > > Alex > > > > > mrs x0, id_aa64pfr0_el1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel