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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id n1sm748614oog.31.2021.03.05.12.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 12:12:18 -0800 (PST) Received: (nullmailer pid 571580 invoked by uid 1000); Fri, 05 Mar 2021 20:12:18 -0000 Date: Fri, 5 Mar 2021 14:12:18 -0600 From: Rob Herring To: Daniel Palmer Cc: Stephen Boyd , DTML , linux-arm-kernel , linux-clk@vger.kernel.org Subject: Re: [RFC PATCH 1/1] dt-bindings: clk: Mstar msc313 clkgen mux Message-ID: <20210305201218.GA568065@robh.at.kernel.org> References: <20210212111649.3251306-1-daniel@0x0f.com> <20210212111649.3251306-2-daniel@0x0f.com> <161317510165.1254594.14810451393733659018@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210305_201221_192135_40B6D59F X-CRM114-Status: GOOD ( 24.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Feb 13, 2021 at 10:18:14AM +0900, Daniel Palmer wrote: > Hi Stephen, > > On Sat, 13 Feb 2021 at 09:11, Stephen Boyd wrote: > > > +examples: > > > + - | > > > + clkgen_mux_mspi0: clkgen_mux_mspi0 { > > > + compatible = "mstar,msc313-clkgen-mux"; > > > + regmap = <&clkgen>; > > > + offset = <0xcc>; > > > + #clock-cells = <1>; > > > + mstar,gate = <0>; > > > + mstar,mux-shift = <2>; > > > + mstar,mux-width = <2>; > > > > It looks like a node-per clk sort of binding which has been rejected > > multiple times in the past. If the clks are spread across various > > devices then it sounds like the mediatek design where they have many > > syscon nodes that also register clks inside those register spaces. In > > this case, I would expect the clkgen node to be registering clks. Given > > that there isn't a reg property and there's these mstar specific > > properties like shift/width it looks really wrong. Please don't do this. > > Ok. I will rethink this. One of the problems I face here is that there > isn't any documentation for what the clkgen looks like. All the more reason to not do a node per clock. > I have a list of offsets and bit positions for these muxes but very little else. > Looking at the mediatek clock drivers it seems like they have a driver > that consumes some register areas and then creates all of the muxes > etc within those areas within the driver instead. If that's an > acceptable solution I will go for that. > There would probably be 2 compatible strings right now (one for the pm > area and one for the normal area) and that would take a phandle to the > syscon that holds the registers. Then there would be a big table of > the offsets, masks etc in the driver. Ideally, the 'syscon' is just the clock provider or a child node is. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel