From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E4B0C433DB for ; Sat, 6 Mar 2021 14:17:30 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21DBC6501A for ; Sat, 6 Mar 2021 14:17:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 21DBC6501A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xAgdd8XBwJQom0gPFn0MSxieiaSlMHnlEReTEBMK32c=; b=h+p9DFIQYCnkgqWlKK+cjEOLh 5dfk+bH4cnMfI03qk0/fbR+eba0viXyJeZca7/4nNLW7xE97TzREOxhT85Go0ZjiKjoMJap6N+/Y+ OfsFU2G72vQOYLAGjy9AqcxTgQaEHlQMt9TbYOb1dR17qtMdv+/GXJcK696JYFlxPRslZ36PWNttL X8lOihR5OU2z96an0lFSM8g62kU1h3i7t3wtsF8WDSQ0PYz5hLfXMI6oSr3rOEZanB3/7CfCo+ll6 WFbEXILu0lVouAOJKZJHY8btQmu45up6v3CXU+R9F1F8wYKqgISeJ0JNgK0c8z2yoYgE4uZRNtdnp eY8mzrRuA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lIXiq-003F30-1v; Sat, 06 Mar 2021 14:16:00 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lIXik-003F2A-Jh for linux-arm-kernel@lists.infradead.org; Sat, 06 Mar 2021 14:15:57 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 545426501A; Sat, 6 Mar 2021 14:15:51 +0000 (UTC) Date: Sat, 6 Mar 2021 14:15:48 +0000 From: Catalin Marinas To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com, James Morse , Julien Thierry , Suzuki K Poulose , Will Deacon , Mark Rutland , Alexandru Elisei Subject: Re: [PATCH] KVM: arm64: Ensure I-cache isolation between vcpus of a same VM Message-ID: <20210306141546.GB2932@arm.com> References: <20210303164505.68492-1-maz@kernel.org> <20210305190708.GL23855@arm.com> <877dmksgaw.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <877dmksgaw.wl-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210306_141554_863197_39102246 X-CRM114-Status: GOOD ( 20.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Mar 06, 2021 at 10:54:47AM +0000, Marc Zyngier wrote: > On Fri, 05 Mar 2021 19:07:09 +0000, > Catalin Marinas wrote: > > > > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > > It recently became apparent that the ARMv8 architecture has interesting > > > rules regarding attributes being used when fetching instructions > > > if the MMU is off at Stage-1. > > > > > > In this situation, the CPU is allowed to fetch from the PoC and > > > allocate into the I-cache (unless the memory is mapped with > > > the XN attribute at Stage-2). > > > > Digging through the ARM ARM is hard. Do we have this behaviour with FWB > > as well? > > The ARM ARM doesn't seem to mention FWB at all when it comes to > instruction fetch, which is sort of expected as it only covers the > D-side. I *think* we could sidestep this when CTR_EL0.DIC is set > though, as the I-side would then snoop the D-side. Not sure this helps. CTR_EL0.DIC refers to the need for maintenance to PoU while the SCTLR_EL1.M == 0 causes the I-cache to fetch from PoC. I don't think I-cache snooping the D-cache would happen to the PoU when the S1 MMU is off. My reading of D4.4.4 is that when SCTLR_EL1.M == 0 both I and D accesses are Normal Non-cacheable with a note in D4.4.6 that Non-cacheable accesses may be held in the I-cache. The FWB rules on combining S1 and S2 says that Normal Non-cacheable at S1 is "upgraded" to cacheable. This should happen irrespective of whether the S1 MMU is on or off and should apply to both I and D accesses (since it does not explicitly says). So I think we could skip this IC IALLU when FWB is present. The same logic should apply when the VMM copies the VM text. With FWB, we probably only need D-cache maintenance to PoU and only if CTR_EL0.IDC==0. I haven't checked what the code currently does. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel