From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: dmaengine@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
Vinod Koul <vkoul@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
Rohit Visavalia <RVISAVAL@xilinx.com>
Subject: [PATCH 1/2] dmaengine: xilinx: dpdma: Fix descriptor issuing on video group
Date: Sun, 7 Mar 2021 06:06:28 +0200 [thread overview]
Message-ID: <20210307040629.29308-2-laurent.pinchart@ideasonboard.com> (raw)
In-Reply-To: <20210307040629.29308-1-laurent.pinchart@ideasonboard.com>
When multiple channels are part of a video group, the transfer is
triggered only when all channels in the group are ready. The logic to do
so is incorrect, as it causes the descriptors for all channels but the
last one in a group to not being pushed to the hardware. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
drivers/dma/xilinx/xilinx_dpdma.c | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c
index 55df63dead8d..d504112c609e 100644
--- a/drivers/dma/xilinx/xilinx_dpdma.c
+++ b/drivers/dma/xilinx/xilinx_dpdma.c
@@ -839,6 +839,7 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
struct xilinx_dpdma_tx_desc *desc;
struct virt_dma_desc *vdesc;
u32 reg, channels;
+ bool first_frame;
lockdep_assert_held(&chan->lock);
@@ -852,14 +853,6 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
chan->running = true;
}
- if (chan->video_group)
- channels = xilinx_dpdma_chan_video_group_ready(chan);
- else
- channels = BIT(chan->id);
-
- if (!channels)
- return;
-
vdesc = vchan_next_desc(&chan->vchan);
if (!vdesc)
return;
@@ -884,13 +877,26 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
upper_32_bits(sw_desc->dma_addr)));
- if (chan->first_frame)
+ first_frame = chan->first_frame;
+ chan->first_frame = false;
+
+ if (chan->video_group) {
+ channels = xilinx_dpdma_chan_video_group_ready(chan);
+ /*
+ * Trigger the transfer only when all channels in the group are
+ * ready.
+ */
+ if (!channels)
+ return;
+ } else {
+ channels = BIT(chan->id);
+ }
+
+ if (first_frame)
reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
else
reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
- chan->first_frame = false;
-
dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
}
--
Regards,
Laurent Pinchart
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next prev parent reply other threads:[~2021-03-07 4:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-07 4:06 [PATCH 0/2] dmaengine: Fix issues in Xilinx dpdma driver Laurent Pinchart
2021-03-07 4:06 ` Laurent Pinchart [this message]
2021-03-07 4:06 ` [PATCH 2/2] dmaengine: xilinx: dpdma: Fix race condition in done IRQ Laurent Pinchart
2021-03-16 10:45 ` [PATCH 0/2] dmaengine: Fix issues in Xilinx dpdma driver Vinod Koul
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