From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0D2DC433DB for ; Thu, 11 Mar 2021 00:10:23 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A12764FC8 for ; Thu, 11 Mar 2021 00:10:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A12764FC8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=z0sJwQULkjS+jbJZ8ieYzT7qxEyqdoJlVBgFCnazIG8=; b=Mzi+kIk/7t4wZNyUs0qvTQuRB qqMjsLwwkgGCrf2bgWLqrlEfvZ18CHh9iBfuIzOOujdpBE+DD2Do7qmMnzQHDat1WeECbNayL37Ot LI1Gcsh/TUX/3SZ1phga3QVHaCnltxQ4Kjn7rRPE854Cb6P5ptDoiT+lDTNnNwlVWMQGTMMUF1f2H iUKakvxcbqVh1YBgM/Bwq0uj7Vdk+f3Q7OIVUNSkYWlByi29grqPRLBKS+vbGitQzzGJ7xrXdbKFi 4xXotFpgaT/pyHYFYYI6Daa4fW54EM89l/vnLGDL/yRa3MTLDmvPKe0dad1EdacD63z5HX5LnsxvF BwI7XBiJg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lK8ss-0082zj-1O; Thu, 11 Mar 2021 00:08:58 +0000 Received: from mail-il1-f174.google.com ([209.85.166.174]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lK8sg-0082wu-2x for linux-arm-kernel@lists.infradead.org; Thu, 11 Mar 2021 00:08:48 +0000 Received: by mail-il1-f174.google.com with SMTP id h18so17356450ils.2 for ; Wed, 10 Mar 2021 16:08:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FOMAKATdifDr6FlmQ9HjwBsrw11qeqE3kI6wm0SfYvU=; b=sJqQaHJy2sHDhWzoEXU/Zqzes6OAXqfecevVepoBOz3WKbXvBz4joNg2YrLV5zSh6s Os/c2UFnphiy+QU8aiKXWXwcwtTjcgeOvwOJD5sayyeDEJlzvyrN9wTJUI8F7kDrYz2d sTFlKOhq7ZVba5831+ht6Z+LLdJ736OkdduDqgXUmpsL0zKIndPwkTPnJyazhgFCZIso bqfVB8XaNWJvzCLA8lTk5a+EU3F7dwmdEQyr+BpEyKNeH7/ai8HzQkcib+DrXDyoiaJc Ny9MpatTaty2PGEtBAyC+M+nM+r1SZIQ4gnKIr64UJm0Db6RKjjrp4brB2E6MVtzjQUS 7lGw== X-Gm-Message-State: AOAM530ibFiOzl4mOUU4nvItu4/2CfJAvdKQT3NbkH9MXTZhrowRSliK InrYjWvCaxq7N0Kn0zs0Vw== X-Google-Smtp-Source: ABdhPJz97I0fuv2LaCHNDEf4YfaxyAwcKHowOMAIRPq0PmZrHkz1RRX7u16P0fIvTQ/db5IMbTHQNw== X-Received: by 2002:a05:6e02:1c83:: with SMTP id w3mr4942092ill.216.1615421325011; Wed, 10 Mar 2021 16:08:45 -0800 (PST) Received: from xps15.herring.priv ([64.188.179.253]) by smtp.googlemail.com with ESMTPSA id x17sm484351ilm.40.2021.03.10.16.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 16:08:44 -0800 (PST) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland Cc: Ian Rogers , Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 01/10] arm64: pmu: Add function implementation to update event index in userpage Date: Wed, 10 Mar 2021 17:08:28 -0700 Message-Id: <20210311000837.3630499-2-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210311000837.3630499-1-robh@kernel.org> References: <20210311000837.3630499-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210311_000846_865782_E3DF2246 X-CRM114-Status: GOOD ( 20.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault In order to be able to access the counter directly for userspace, we need to provide the index of the counter using the userpage. We thus need to override the event_idx function to retrieve and convert the perf_event index to armv8 hardware index. Since the arm_pmu driver can be used by any implementation, even if not armv8, two components play a role into making sure the behaviour is correct and consistent with the PMU capabilities: * the ARMPMU_EL0_RD_CNTR flag which denotes the capability to access counter from userspace. * the event_idx call back, which is implemented and initialized by the PMU implementation: if no callback is provided, the default behaviour applies, returning 0 as index value. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- arch/arm64/kernel/perf_event.c | 18 ++++++++++++++++++ include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4658fcf88c2b..387838496955 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -871,6 +871,22 @@ static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, clear_bit(idx - 1, cpuc->used_mask); } +static int armv8pmu_access_event_idx(struct perf_event *event) +{ + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR)) + return 0; + + /* + * We remap the cycle counter index to 32 to + * match the offset applied to the rest of + * the counter indices. + */ + if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) + return 32; + + return event->hw.idx; +} + /* * Add an event filter to a given event. */ @@ -1098,6 +1114,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->set_event_filter = armv8pmu_set_event_filter; cpu_pmu->filter_match = armv8pmu_filter_match; + cpu_pmu->pmu.event_idx = armv8pmu_access_event_idx; + cpu_pmu->name = name; cpu_pmu->map_event = map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 505480217cf1..d29aa981d989 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Allow access to hardware counter from userspace */ +#define ARMPMU_EL0_RD_CNTR 2 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel