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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id u9sm17260832pgc.59.2021.03.29.11.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 11:43:23 -0700 (PDT) Date: Mon, 29 Mar 2021 11:43:23 -0700 From: Kees Cook To: Thomas Gleixner Cc: Elena Reshetova , x86@kernel.org, Andy Lutomirski , Peter Zijlstra , Catalin Marinas , Will Deacon , Mark Rutland , Alexander Potapenko , Alexander Popov , Ard Biesheuvel , Jann Horn , Vlastimil Babka , David Hildenbrand , Mike Rapoport , Andrew Morton , Jonathan Corbet , Randy Dunlap , kernel-hardening@lists.openwall.com, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 4/6] x86/entry: Enable random_kstack_offset support Message-ID: <202103291141.EC2A77731@keescook> References: <20210319212835.3928492-1-keescook@chromium.org> <20210319212835.3928492-5-keescook@chromium.org> <87h7kvcqen.ffs@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87h7kvcqen.ffs@nanos.tec.linutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210329_194334_758580_82C1FA07 X-CRM114-Status: GOOD ( 15.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Mar 28, 2021 at 04:18:56PM +0200, Thomas Gleixner wrote: > On Fri, Mar 19 2021 at 14:28, Kees Cook wrote: > > + > > + /* > > + * x86_64 stack alignment means 3 bits are ignored, so keep > > + * the top 5 bits. x86_32 needs only 2 bits of alignment, so > > + * the top 6 bits will be used. > > + */ > > + choose_random_kstack_offset(rdtsc() & 0xFF); > > Comment mumbles about 5/6 bits and the TSC value is masked with 0xFF and > then the applied offset is itself limited with 0x3FF. > > Too many moving parts for someone who does not have the details of all > this memorized. Each piece is intentional -- I will improve the comments to explain each level of masking happening (implicit compiler stack alignment mask, explicit per-arch mask, and the VLA upper-bound protection mask). -- Kees Cook _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel