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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id v30sm4430627otb.23.2021.03.29.06.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 06:58:40 -0700 (PDT) Received: (nullmailer pid 2477089 invoked by uid 1000); Mon, 29 Mar 2021 13:58:38 -0000 Date: Mon, 29 Mar 2021 08:58:38 -0500 From: Rob Herring To: Zhiyong Tao Cc: linus.walleij@linaro.org, mark.rutland@arm.com, matthias.bgg@gmail.com, sean.wang@kernel.org, srv_heupstream@mediatek.com, hui.liu@mediatek.com, eddie.huang@mediatek.com, jg_poxu@mediatek.com, biao.huang@mediatek.com, hongzhou.yang@mediatek.com, erin.lo@mediatek.com, sean.wang@mediatek.com, seiya.wang@mediatek.com, sj.huang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document Message-ID: <20210329135838.GA2473026@robh.at.kernel.org> References: <20210329065047.8388-1-zhiyong.tao@mediatek.com> <20210329065047.8388-3-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210329065047.8388-3-zhiyong.tao@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210329_145858_054808_A1710ADD X-CRM114-Status: GOOD ( 22.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 29, 2021 at 02:50:43PM +0800, Zhiyong Tao wrote: > The commit adds mt8195 compatible node in binding document. > > Signed-off-by: Zhiyong Tao > --- > .../bindings/pinctrl/pinctrl-mt8195.yaml | 152 ++++++++++++++++++ > 1 file changed, 152 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml > new file mode 100644 > index 000000000000..7915b9568c29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml > @@ -0,0 +1,152 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek MT8195 Pin Controller > + > +maintainers: > + - Sean Wang > + > +description: | > + The Mediatek's Pin controller is used to control SoC pins. > + > +properties: > + compatible: > + const: mediatek,mt8195-pinctrl > + > + gpio-controller: true > + > + '#gpio-cells': > + description: | > + Number of cells in GPIO specifier. Since the generic GPIO binding is used, > + the amount of cells must be specified as 2. See the below > + mentioned gpio binding representation for description of particular cells. > + const: 2 > + > + gpio-ranges: > + description: gpio valid number range. > + maxItems: 1 > + > + reg: > + description: | > + Physical address base for gpio base registers. There are 8 GPIO > + physical address base in mt8195. > + maxItems: 8 > + > + reg-names: > + description: | > + Gpio base register names. > + maxItems: 8 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 2 > + > + interrupts: > + description: The interrupt outputs to sysirq. > + maxItems: 1 > + > +#PIN CONFIGURATION NODES > +patternProperties: > + '^pins': Normally we're doing '-pins$'. > + type: object > + description: | > + A pinctrl node should contain at least one subnodes representing the > + pinctrl groups available on the machine. Each subnode will list the > + pins it needs, and how they should be configured, with regard to muxer > + configuration, pullups, drive strength, input enable/disable and > + input schmitt. > + An example of using macro: > + pincontroller { > + /* GPIO0 set as multifunction GPIO0 */ > + state_0_node_a { Use the node name pattern defined. > + pinmux = ; > + }; > + /* GPIO1 set as multifunction CLKM1 */ > + state_0_node_b { > + pinmux = ; > + }; > + }; > + $ref: "pinmux-node.yaml" > + > + properties: > + pinmux: > + description: | > + Integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are defined > + as macros in dt-bindings/pinctrl/-pinfunc.h directly. > + > + drive-strength: > + description: | > + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See > + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8195. > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > + > + bias-pull-down: true > + > + bias-pull-up: true > + > + bias-disable: true > + > + output-high: true > + > + output-low: true > + > + input-enable: true > + > + input-disable: true > + > + input-schmitt-enable: true > + > + input-schmitt-disable: true > + > + required: > + - pinmux > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-controller > + - '#interrupt-cells' > + - gpio-controller > + - '#gpio-cells' > + - gpio-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8195-pinctrl"; > + reg = <0x10005000 0x1000>, > + <0x11d10000 0x1000>, > + <0x11d30000 0x1000>, > + <0x11d40000 0x1000>, > + <0x11e20000 0x1000>, > + <0x11e20000 0x1000>, > + <0x11eb0000 0x1000>, > + <0x11f40000 0x1000>, > + <0x1000b000 0x1000>; > + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", > + "iocfg_br", "iocfg_lm", "iocfg_rb", > + "iocfg_tl", "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 144>; > + interrupt-controller; > + interrupts = ; > + #interrupt-cells = <2>; > + > + pins { > + pinmux = ; > + output-low; > + }; > + }; > -- > 2.18.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel