From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F391AC433C1 for ; Tue, 30 Mar 2021 07:44:59 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83E2161929 for ; Tue, 30 Mar 2021 07:44:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83E2161929 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=nxn7lVJ0zkmqsFpqcF42AjSEZmZaxUNLTJbrez6rvY0=; b=CzQmNVNfX80z2n3AwOLNffme49 jHDN1j/4Osoq9XlaZ6RaYJ2vB1JbWJl3oSyudN4GhtIxlHxGOzMMuIQGF+EC2wv5WNY+HK/XUqNyR E7FmgEe+8GFyNX2gDJP3cd30pXRi3F4pVKO5UkanegaPH/eGGNmRq6/0c6N2TqlVf4s6O2kK6Jk2u 6a4WJexEWQ7XUIn5FwfYxGGjAq4NucfvIxsFo4mmjAreID2f9wsRmyi9fN5Fpa8AEnPG9Aysk2otV LJ477pEkKt2iMAfoWTuyh7isYaXpDAyg0fPKqmX4lc8Ic/7chLwPAkKlY5LQR73zYQ2rXNVF4+BRY Sk/YiCoA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lR91b-002x0r-Ae; Tue, 30 Mar 2021 07:42:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lR91X-002x0V-GF for linux-arm-kernel@lists.infradead.org; Tue, 30 Mar 2021 07:42:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6CADEED1; Tue, 30 Mar 2021 00:42:46 -0700 (PDT) Received: from net-arm-thunderx2-02.shanghai.arm.com (net-arm-thunderx2-02.shanghai.arm.com [10.169.208.215]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 322403F719; Tue, 30 Mar 2021 00:42:40 -0700 (PDT) From: Jianlin Lv To: bpf@vger.kernel.org Cc: zlim.lnx@gmail.com, catalin.marinas@arm.com, will@kernel.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, kafai@fb.com, songliubraving@fb.com, yhs@fb.com, john.fastabend@gmail.com, kpsingh@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jianlin.Lv@arm.com, iecedge@gmail.com Subject: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn Date: Tue, 30 Mar 2021 15:42:35 +0800 Message-Id: <20210330074235.525747-1-Jianlin.Lv@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_084251_942269_DFAE0C69 X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A64_MOV is currently mapped to Add Instruction. Architecturally MOV (register) is an alias of ORR (shifted register) and MOV (to or from SP) is an alias of ADD (immediate). This patch redefines A64_MOV and uses existing functionality aarch64_insn_gen_move_reg() in insn.c to encode MOV (register) instruction. For moving between register and stack pointer, rename macro to A64_MOV_SP. Test: modprobe test_bpf test_name="SPILL_FILL" bpf_jit_disasm -o without patch: 0: stp x29, x30, [sp, #-16]! fd 7b bf a9 4: mov x29, sp fd 03 00 91 ... 14: mov x25, sp f9 03 00 91 ... 24: add x19, x0, #0x0 13 00 00 91 ... 8c: add x0, x7, #0x0 e0 00 00 91 with patch: 0: stp x29, x30, [sp, #-16]! fd 7b bf a9 4: mov x29, sp fd 03 00 91 ... 14: mov x25, sp f9 03 00 91 ... 24: mov x19, x0 f3 03 00 aa ... 8c: mov x0, x7 e0 03 07 aa Signed-off-by: Jianlin Lv --- arch/arm64/net/bpf_jit.h | 7 +++++-- arch/arm64/net/bpf_jit_comp.c | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h index cc0cf0f5c7c3..a2c3cddb1d2f 100644 --- a/arch/arm64/net/bpf_jit.h +++ b/arch/arm64/net/bpf_jit.h @@ -108,8 +108,8 @@ #define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12) /* Rn - imm12; set condition flags */ #define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12) -/* Rd = Rn */ -#define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) +/* Rd = Rn; MOV (to/from SP) */ +#define A64_MOV_SP(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) /* Bitfield move */ #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \ @@ -134,6 +134,9 @@ #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15) #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31) +/* Rd = Rm; MOV (register) */ +#define A64_MOV(sf, Rd, Rm) aarch64_insn_gen_move_reg(Rd, Rm, A64_VARIANT(sf)) + /* Move wide (immediate) */ #define A64_MOVEW(sf, Rd, imm16, shift, type) \ aarch64_insn_gen_movewide(Rd, imm16, shift, \ diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index f7b194878a99..2a118c0fcb30 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -229,7 +229,7 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) /* Save FP and LR registers to stay align with ARM64 AAPCS */ emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); - emit(A64_MOV(1, A64_FP, A64_SP), ctx); + emit(A64_MOV_SP(1, A64_FP, A64_SP), ctx); /* Save callee-saved registers */ emit(A64_PUSH(r6, r7, A64_SP), ctx); @@ -237,7 +237,7 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) emit(A64_PUSH(fp, tcc, A64_SP), ctx); /* Set up BPF prog stack base register */ - emit(A64_MOV(1, fp, A64_SP), ctx); + emit(A64_MOV_SP(1, fp, A64_SP), ctx); if (!ebpf_from_cbpf) { /* Initialize tail_call_cnt */ -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel