From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACA39C433B4 for ; Wed, 31 Mar 2021 15:40:50 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 529286101D for ; Wed, 31 Mar 2021 15:40:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 529286101D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=81HVZ7Ss055BupIjKF0dbldJMrV8n6bJGnPdhX67Yc8=; b=TxfCtwyxDww09vNcNDEuSqH3Z DxXe3VGfQR7Favrq/MF/MqWA1ThIzEgM+q1qK8tju1v6olKNII/2sZqsYVhGoz/7+JgK/lxOpwnIu Hp01fQAAn2ZYhNM1avYduID9rEHQcBflsp43Op66BEvj7j1MClr6xCN6VWzA/c9WSkTZXnS03a62I 4gpOQLekLDFkB0A9QGFFDBf+frLvR4ky0ukXfwNKgEyTlombibDIScJB1fd05vkCwrJ2BBPwkkhch yQAasEGqi6fBKKS+whO6PJuXFqIqJm+82Crwl/0AkNgetYWY8LkdAstzeKbAWLWjwrtlVFlmehMLh owLh1HsKA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRcwC-006vq7-Hl; Wed, 31 Mar 2021 15:39:20 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRcvl-006vgj-TH for linux-arm-kernel@lists.infradead.org; Wed, 31 Mar 2021 15:38:57 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6CF1D60FED; Wed, 31 Mar 2021 15:38:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617205132; bh=zSKNNt8aHpVOX7T1mrGusbLW0X9P8mDEBnTRjCK5rWs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kXb8HMKzNCMDmWEsyoz6cYK42VRs7763h3dgrABPa04VRqfZx0PIX+QlCr3xM30bG FXGIk8u9jl0Ks0KwB4Vtqqh4HJuhOOIM2TwuZ2lLhC35GkLsZwH+tGLxETrlvB/Xbq rN60C/MqtfB4tnmo9f1b3sCq8P/hOCh1F56NdYn9UWpHMpLb/Ts6vEPDWrIu7JDKfD nD8lMH5xZ7mm7ZK0sSTktM/1hcsEMINzyxc2toeRFA0hogjvHlXyX6dj2xYZV13N8S 8hE3OIteR2wcc+0ePV3Zkros/1XNZERWRn0EhiQ/XTxMHZoNN3uXyg5zuRuYDQHm8w lF9TNTJX//avw== Date: Wed, 31 Mar 2021 16:38:46 +0100 From: Will Deacon To: Rob Herring Cc: Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland , Ian Rogers , Alexander Shishkin , Honnappa Nagarahalli , Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 02/10] arm64: perf: Enable PMU counter direct access for perf event Message-ID: <20210331153845.GB7815@willie-the-truck> References: <20210311000837.3630499-1-robh@kernel.org> <20210311000837.3630499-3-robh@kernel.org> <20210330153125.GC6567@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210331_163855_634829_0833C4D9 X-CRM114-Status: GOOD ( 22.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 30, 2021 at 04:08:11PM -0500, Rob Herring wrote: > On Tue, Mar 30, 2021 at 12:09 PM Rob Herring wrote: > > On Tue, Mar 30, 2021 at 10:31 AM Will Deacon wrote: > > > The logic here feels like it > > > could with a bit of untangling. > > > > Yes, I don't love it, but couldn't come up with anything better. It is > > complicated by the fact that flags have to be set before we assign the > > counter and can't set/change them when we assign the counter. It would > > take a lot of refactoring with armpmu code to fix that. > > How's this instead?: > > if (armv8pmu_event_want_user_access(event) || !armv8pmu_event_is_64bit(event)) > event->hw.flags |= ARMPMU_EL0_RD_CNTR; > > /* > * At this point, the counter is not assigned. If a 64-bit counter is > * requested, we must make sure the h/w has 64-bit counters if we set > * the event size to 64-bit because chaining is not supported with > * userspace access. This may still fail later on if the CPU cycle > * counter is in use. > */ > if (armv8pmu_event_is_64bit(event) && > (!armv8pmu_event_want_user_access(event) || > armv8pmu_has_long_event(cpu_pmu) || (hw_event_id == > ARMV8_PMUV3_PERFCTR_CPU_CYCLES))) > event->hw.flags |= ARMPMU_EVT_64BIT; I thought there were some cases where we could assign cycles event to an event counter; does that not happen anymore? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel