From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 769E8C433B4 for ; Thu, 1 Apr 2021 09:06:06 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EAE71606A5 for ; Thu, 1 Apr 2021 09:06:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EAE71606A5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=u1WZcy1HMgWWU5g9IzEGuHDva4+4iya364jqTouui/Y=; b=MSSg3nuLXwVkR9e4auxZQemRS ZOsU+Xb/MK5b1cYFnCyP4PBOmM6ku3c+0qsrgKkPX664/MOY/4RcDJsofeOJW6pv/D9wsck6RwNg2 XffROMyrInwiVl9zyic9N6PNagU+u4bqliYChtHkVrnwYgnnmGIzc4DTR+d1OCYWpAND9NH9Yreeq WfyYDbGubIZf5q8lM1wb6mQK6LiXCTzk8OzWY3PxRrtqjqKCyD0vWih2/1Edcm5cx27JdeBUIA/2J Hl5x64cfGNJZW1J1qZ+f+6HL6dF6gkiNrviHi3uD4dGtR23CSzPVpC0Fm8zED+hVS7jc5edGnUivq hSqhowdmg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRtFo-0090cJ-Iw; Thu, 01 Apr 2021 09:04:40 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRtFj-0090bm-T3 for linux-arm-kernel@lists.infradead.org; Thu, 01 Apr 2021 09:04:38 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5C408610A5; Thu, 1 Apr 2021 09:04:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617267874; bh=muveIZy9ANXdY0khfktn7mV+Le3qqWgit/n0uDMsFok=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jRRMVerETfm1pofEK4SDc+PwF4vXH+mM6kDKa3yiEq6qjeWIcbz/812P6ebUyXTKe EmGgnmCCyfggYtjBeH+mkG77YN0ummtOhR/7wvYS44OIYLHtHBXOQ3DjS8mpfwHixN PkeihXAuLq2jfEoj2QPRqqm/jhlG40pAdZ4+NV81oFHi09g9ol2Zp5FZxsEaVZyGpq qtiSzk+18tbyH8LSo++b9bihBOWULevV4t74WKk5THWfvpe+Ya7W1hYzrsvP+Bdc67 D1QY+AAxov95hqjKE0GmIjcAfqCPwm4FFSIB0SvvCv8IiOVdVT0YU9NWseSYLMf6za yNTq0sBzhKFgg== Date: Thu, 1 Apr 2021 10:04:28 +0100 From: Will Deacon To: Rob Herring Cc: Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland , Ian Rogers , Alexander Shishkin , Honnappa Nagarahalli , Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6 02/10] arm64: perf: Enable PMU counter direct access for perf event Message-ID: <20210401090427.GB8781@willie-the-truck> References: <20210311000837.3630499-1-robh@kernel.org> <20210311000837.3630499-3-robh@kernel.org> <20210330153125.GC6567@willie-the-truck> <20210331153845.GB7815@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_100436_472410_C6043970 X-CRM114-Status: GOOD ( 29.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 31, 2021 at 12:52:11PM -0500, Rob Herring wrote: > On Wed, Mar 31, 2021 at 10:38 AM Will Deacon wrote: > > > > On Tue, Mar 30, 2021 at 04:08:11PM -0500, Rob Herring wrote: > > > On Tue, Mar 30, 2021 at 12:09 PM Rob Herring wrote: > > > > On Tue, Mar 30, 2021 at 10:31 AM Will Deacon wrote: > > > > > The logic here feels like it > > > > > could with a bit of untangling. > > > > > > > > Yes, I don't love it, but couldn't come up with anything better. It is > > > > complicated by the fact that flags have to be set before we assign the > > > > counter and can't set/change them when we assign the counter. It would > > > > take a lot of refactoring with armpmu code to fix that. > > > > > > How's this instead?: > > > > > > if (armv8pmu_event_want_user_access(event) || !armv8pmu_event_is_64bit(event)) > > > event->hw.flags |= ARMPMU_EL0_RD_CNTR; > > > > > > /* > > > * At this point, the counter is not assigned. If a 64-bit counter is > > > * requested, we must make sure the h/w has 64-bit counters if we set > > > * the event size to 64-bit because chaining is not supported with > > > * userspace access. This may still fail later on if the CPU cycle > > > * counter is in use. > > > */ > > > if (armv8pmu_event_is_64bit(event) && > > > (!armv8pmu_event_want_user_access(event) || > > > armv8pmu_has_long_event(cpu_pmu) || (hw_event_id == > > > ARMV8_PMUV3_PERFCTR_CPU_CYCLES))) > > > event->hw.flags |= ARMPMU_EVT_64BIT; > > > > I thought there were some cases where we could assign cycles event to an > > event counter; does that not happen anymore? > > Yes, but if we hit that scenario when the user has asked for 64-bit > user access, then we return an error later when assigning the counter. > I think we can assume if users have gone to the trouble of requesting > 64-bit counters, then they can deal with ensuring they don't have > multiple users. > > Otherwise, the only way I see to simplify this is we only support > 64-bit counters in userspace when we have v8.5 PMU. I'm happy to start from that position, and then we can extend it later if there's a need. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel