From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9278C433ED for ; Thu, 1 Apr 2021 11:35:34 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1741610D1 for ; Thu, 1 Apr 2021 11:35:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E1741610D1 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AYcOsOURu6tHsuvtDZU7gjBvWRYSW3XtJcFISyWRSak=; b=qWQc4OQE7wdKbnI+aobwF3Wd8 XO3y/7+P/BSPpaXNX0nmGwnZzh/uWR/nsjJQF4RBg30rAR6saZODhDLHWIrGeHa1ZMMvfpD84DrdY yC00E2iMNmIERReSxdkpwhnpF606VkaoK0TVe22Sl3zcXrTEEKWL2scaCs7B6nHkxf+JqIJZkqVkQ tR5hB70MfCOlKetGZQbXewWLE6KUktHOFcCBeuhrpZLElFrCIkxqi55RLUaullv4GPNQ4JRRiw9Gy 9iiyaQHocyiFg3keY04khVs1WaayM9S9M24YmYWVm3xddlh6UNBFskGfpV7tmuex2IY5ihOPE75Ax sZI1noRBA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRva9-009T65-9f; Thu, 01 Apr 2021 11:33:49 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRvYS-009SP9-H0 for linux-arm-kernel@lists.infradead.org; Thu, 01 Apr 2021 11:32:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617276724; x=1648812724; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eEFZK/hSf05itEILHRf197/MjzOOVQu1dFzDN6v4vnA=; b=Czunv35bCcWlEYD3lfwjoeCvk8NkBu6FCUvUFeCwF3LdiOqwvibYK7bO NCN8ocfTwVSTsRird4f9HYdmkGV9ajpnNMpqNBn7pB8jHKTGBe1nGV9AX WG6VfOaultHrFHRiZjaPGqo7Q7XUUfDvayBDFlZ8De35SfPNk2sDu0jRv 89kEmgadZ24Z3dV1B0PskvPoeVDL9CBP5HnTeH9u3riRU0o+IAhZBWzra UAqzr3T+xwSeQ/1t5zPFxs+tCWg/LnSeCsy7dLknMwbVPFiTp9nvzzZIK h5ZWgOMUigEuw1H0UZ3Re17fExiH6xGXN8ulJeo8kjgfszpz40acGS7Cd Q==; IronPort-SDR: HXfZ9RMzmQjY7CuO+/qpFKoOhz+m28Oeg8dpY2G2rHfoLKAYBag7LxIp4ci6VTGpOCshYztolJ AVukyjYm+Mm9D7b6DRwUiBZQ3JVcDjcnz1MT8ypGmZB11yTAMdhzu4oGLZhk3E+Amp5+vmzU0j QVndBs0/7kPXOg8/BmyhFCSrDhMVyZLTg8y1MOh8qPo8J/X3g5M3ze2RPaKSNOokSmRt9lcu3k ltl9hgts9btbSUl9KsBk1UqII7d/PCCpZPUcif7ZbHnM3OyFEILY8fw2Pq8QoHG5xF9EQ/bgiE ma0= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132659" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:32:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:32:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:31:46 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 17/30] media: atmel: atmel-isc: add register description for additional modules Date: Thu, 1 Apr 2021 14:27:10 +0300 Message-ID: <20210401112723.189107-18-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_123205_137325_8D22F04A X-CRM114-Status: UNSURE ( 7.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add register description for additional pipeline modules: the Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index a15c13e1a833..457eed74cda9 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -90,6 +90,46 @@ #define ISC_INT_DDONE BIT(8) #define ISC_INT_HISDONE BIT(12) +/* ISC DPC Control Register */ +#define ISC_DPC_CTRL 0x40 + +#define ISC_DPC_CTRL_DPCEN BIT(0) +#define ISC_DPC_CTRL_GDCEN BIT(1) +#define ISC_DPC_CTRL_BLCEN BIT(2) + +/* ISC DPC Config Register */ +#define ISC_DPC_CFG 0x44 + +#define ISC_DPC_CFG_BAYSEL_SHIFT 0 + +#define ISC_DPC_CFG_EITPOL BIT(4) + +#define ISC_DPC_CFG_TA_ENABLE BIT(14) +#define ISC_DPC_CFG_TC_ENABLE BIT(13) +#define ISC_DPC_CFG_TM_ENABLE BIT(12) + +#define ISC_DPC_CFG_RE_MODE BIT(17) + +#define ISC_DPC_CFG_GDCCLP_SHIFT 20 +#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) + +#define ISC_DPC_CFG_BLOFF_SHIFT 24 +#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) + +#define ISC_DPC_CFG_BAYCFG_SHIFT 0 +#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) +/* ISC DPC Threshold Median Register */ +#define ISC_DPC_THRESHM 0x48 + +/* ISC DPC Threshold Closest Register */ +#define ISC_DPC_THRESHC 0x4C + +/* ISC DPC Threshold Average Register */ +#define ISC_DPC_THRESHA 0x50 + +/* ISC DPC STatus Register */ +#define ISC_DPC_SR 0x54 + /* ISC White Balance Control Register */ #define ISC_WB_CTRL 0x00000058 @@ -153,6 +193,33 @@ /* ISC_Gamma Correction Green Entry Register */ #define ISC_GAM_RENTRY 0x00000298 +/* ISC VHXS Control Register */ +#define ISC_VHXS_CTRL 0x398 + +/* ISC VHXS Source Size Register */ +#define ISC_VHXS_SS 0x39C + +/* ISC VHXS Destination Size Register */ +#define ISC_VHXS_DS 0x3A0 + +/* ISC Vertical Factor Register */ +#define ISC_VXS_FACT 0x3a4 + +/* ISC Horizontal Factor Register */ +#define ISC_HXS_FACT 0x3a8 + +/* ISC Vertical Config Register */ +#define ISC_VXS_CFG 0x3ac + +/* ISC Horizontal Config Register */ +#define ISC_HXS_CFG 0x3b0 + +/* ISC Vertical Tap Register */ +#define ISC_VXS_TAP 0x3b4 + +/* ISC Horizontal Tap Register */ +#define ISC_HXS_TAP 0x434 + /* Offset for CSC register specific to sama5d2 product */ #define ISC_SAMA5D2_CSC_OFFSET 0 -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel