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Miller" Subject: Re: Bogus struct page layout on 32-bit Message-ID: <20210411223537.GF2531743@casper.infradead.org> References: <20210409185105.188284-3-willy@infradead.org> <202104100656.N7EVvkNZ-lkp@intel.com> <20210410024313.GX2531743@casper.infradead.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Apr 10, 2021 at 09:10:47PM +0200, Arnd Bergmann wrote: > On Sat, Apr 10, 2021 at 4:44 AM Matthew Wilcox wrote: > > + dma_addr_t dma_addr __packed; > > }; > > struct { /* slab, slob and slub */ > > union { > > > > but I don't know if GCC is smart enough to realise that dma_addr is now > > on an 8 byte boundary and it can use a normal instruction to access it, > > or whether it'll do something daft like use byte loads to access it. > > > > We could also do: > > > > + dma_addr_t dma_addr __packed __aligned(sizeof(void *)); > > > > and I see pahole, at least sees this correctly: > > > > struct { > > long unsigned int _page_pool_pad; /* 4 4 */ > > dma_addr_t dma_addr __attribute__((__aligned__(4))); /* 8 8 */ > > } __attribute__((__packed__)) __attribute__((__aligned__(4))); > > > > This presumably affects any 32-bit architecture with a 64-bit phys_addr_t > > / dma_addr_t. Advice, please? > > I've tried out what gcc would make of this: https://godbolt.org/z/aTEbxxbG3 > > struct page { > short a; > struct { > short b; > long long c __attribute__((packed, aligned(2))); > } __attribute__((packed)); > } __attribute__((aligned(8))); > > In this structure, 'c' is clearly aligned to eight bytes, and gcc does > realize that > it is safe to use the 'ldrd' instruction for 32-bit arm, which is forbidden on > struct members with less than 4 byte alignment. However, it also complains > that passing a pointer to 'c' into a function that expects a 'long long' is not > allowed because alignof(c) is only '2' here. > > (I used 'short' here because I having a 64-bit member misaligned by four > bytes wouldn't make a difference to the instructions on Arm, or any other > 32-bit architecture I can think of, regardless of the ABI requirements). So ... we could do this: +++ b/include/linux/types.h @@ -140,7 +140,7 @@ typedef u64 blkcnt_t; * so they don't care about the size of the actual bus addresses. */ #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT -typedef u64 dma_addr_t; +typedef u64 __attribute__((aligned(sizeof(void *)))) dma_addr_t; #else typedef u32 dma_addr_t; #endif but I'm a little scared that this might have unintended consequences. And Jesper points out that a big-endian 64-bit dma_addr_t can impersonate a PageTail page, and we should solve that problem while we're at it. So I don't think we should do this, but thought I should mention it as a possibility. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel