From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F39AC433B4 for ; Tue, 20 Apr 2021 03:17:37 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C473761220 for ; Tue, 20 Apr 2021 03:17:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C473761220 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AmhPIyWAi7/E9tNy9cTuLvREX0EOTaGLqyKJvzSVqFs=; b=CT+f5DqEP4J7CJ7PuE/u0cfsd GZMZuc66s1zFmtDqQ0JqRRkGf+Cc5gLlG/V8JuTP3B4y7XjCyF1XFtH3u2aH67qPahfhCUBkBiHX5 iDY5zqVOfAqAsgXZGXoBnK3QewVoK9eKk7U3zFxuFHPDkHIUapRP0/34tldKqI56Gg67AGU3gMF3V tO9VVIfHHxXAaW8Bi8+L+nPQoYOMiTOpim+1rSklVGMFSGJOcu4gf1eFwVRAbBROi35AOwOdiDx6y 0DPneLc0gv00VrR2ZK5gT1fNJoabdSZqWgsfyq1yfSScjNo6ABFOl/2HLpb4A7kWsqA2li1II5REa fZl9JCy0g==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lYgrX-00B39H-4k; Tue, 20 Apr 2021 03:15:43 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lYgrD-00B379-CN for linux-arm-kernel@desiato.infradead.org; Tue, 20 Apr 2021 03:15:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=aXUK1/r7k93rzxf4EUlsML+9TguQHlwah2y8W6FnseA=; b=eHkRlSUFUdCMzrR17Wia3N7EyB YkTxZZGfYS2odWD5BKIB35m4Ej9f/9sfL9FONNyVzsC5Gu7plOksXsbnyUNfa4nh75hfXzdpQcFGr bRngAypzZQIvb4kA2q+58QgnlKWv/yFubwYL/JSDzp9pSZX/IX1q/GHzPWeEbuppT4PolNho9L98D FFbKwg/kht4616Kd+CPvBjY/7x0IodBcBGOfdGpWBEof2W6utdZ1/3756nrQpGm5mVCXcIW88jAph S9sCsvuvH/XoqMW51ASDVkwEb+tIlgeFybOtl5hSqnB3e4XBGDGp9Z4wl6VAmk7sQGWFEGSbqndg3 3LHGMKoQ==; Received: from mail-oi1-f174.google.com ([209.85.167.174]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lYgr8-00BmhL-OT for linux-arm-kernel@lists.infradead.org; Tue, 20 Apr 2021 03:15:22 +0000 Received: by mail-oi1-f174.google.com with SMTP id u16so20313519oiu.7 for ; Mon, 19 Apr 2021 20:15:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aXUK1/r7k93rzxf4EUlsML+9TguQHlwah2y8W6FnseA=; b=OPT+SFCPsXK+HwyiRd9f7+amPqb2K6VVrXAvMQtaRh8B7LG1V9RKtvFkXv4hdvSl3m H7aeeV2gQbqJn4MoJLJe5mGzodrZtEAnRCW4OdtoKywd872+5c0qptwWGWz6AU0x8DLC 6mOML2XvoSRyo1sqkKD5gQHFRGiAluclzy/Hq86s3TDlIXDh3gM6REkhxyUCix9csvnY BxWwNz0V23Zwaakxbpduzn5+Xuo81l3tOhCUILoIG7D3ok4fEnS/3oBmWaIHUHBFGi0l l/XwPlrG01POCwnZDT7MBh8BpYnYSfX5T7blMSmcuFhw2pCkCLXRCyNmahK8VeJyIv8c fKiQ== X-Gm-Message-State: AOAM532ji9Xd4gUk4e6zj3YiIhgq0tVRluWs8UCREKXCY54gPFLeX/JW Eh5s8PcRcaEA0RK7y6aIVTG472bf2g== X-Google-Smtp-Source: ABdhPJxc6noVLD8p09Y2t8apB4dpVBJ9wZwwPuIYcud3i6iK2GH9f9h178dgJb9r9GD2Bh1MZE4swA== X-Received: by 2002:aca:cf09:: with SMTP id f9mr1581273oig.95.1618888517747; Mon, 19 Apr 2021 20:15:17 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g16sm2347896oof.43.2021.04.19.20.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 20:15:16 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland Cc: Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/9] arm64: pmu: Add function implementation to update event index in userpage Date: Mon, 19 Apr 2021 22:15:04 -0500 Message-Id: <20210420031511.2348977-3-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210420031511.2348977-1-robh@kernel.org> References: <20210420031511.2348977-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210419_201518_818414_FBC88DC4 X-CRM114-Status: GOOD ( 22.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault In order to be able to access the counter directly for userspace, we need to provide the index of the counter using the userpage. We thus need to override the event_idx function to retrieve and convert the perf_event index to armv8 hardware index. Since the arm_pmu driver can be used by any implementation, even if not armv8, two components play a role into making sure the behaviour is correct and consistent with the PMU capabilities: * the ARMPMU_EL0_RD_CNTR flag which denotes the capability to access counter from userspace. * the event_idx call back, which is implemented and initialized by the PMU implementation: if no callback is provided, the default behaviour applies, returning 0 as index value. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v7: - Add define ARMV8_IDX_CYCLE_COUNTER_USER for userspace index of cycle counter --- arch/arm64/kernel/perf_event.c | 20 +++++++++++++++++++- include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4658fcf88c2b..40cf59455ce8 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -332,7 +332,7 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { */ #define ARMV8_IDX_CYCLE_COUNTER 0 #define ARMV8_IDX_COUNTER0 1 - +#define ARMV8_IDX_CYCLE_COUNTER_USER 32 /* * We unconditionally enable ARMv8.5-PMU long event counter support @@ -871,6 +871,22 @@ static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, clear_bit(idx - 1, cpuc->used_mask); } +static int armv8pmu_access_event_idx(struct perf_event *event) +{ + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR)) + return 0; + + /* + * We remap the cycle counter index to 32 to + * match the offset applied to the rest of + * the counter indices. + */ + if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) + return ARMV8_IDX_CYCLE_COUNTER_USER; + + return event->hw.idx; +} + /* * Add an event filter to a given event. */ @@ -1098,6 +1114,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->set_event_filter = armv8pmu_set_event_filter; cpu_pmu->filter_match = armv8pmu_filter_match; + cpu_pmu->pmu.event_idx = armv8pmu_access_event_idx; + cpu_pmu->name = name; cpu_pmu->map_event = map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 505480217cf1..d29aa981d989 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Allow access to hardware counter from userspace */ +#define ARMPMU_EL0_RD_CNTR 2 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel