From: "Pali Rohár" <pali@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Jianjun Wang <jianjun.wang@mediatek.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, Marc Zyngier <maz@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, youlin.pei@mediatek.com,
chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com,
sin_jieyang@mediatek.com, drinkcat@chromium.org,
Rex-BC.Chen@mediatek.com, anson.chuang@mediatek.com,
Krzysztof Wilczyski <kw@linux.com>
Subject: Re: [PATCH v10 5/7] PCI: mediatek-gen3: Add MSI support
Date: Tue, 20 Apr 2021 11:44:02 +0200 [thread overview]
Message-ID: <20210420094402.hwdkbspl5wu4rtex@pali> (raw)
In-Reply-To: <20210420061723.989-6-jianjun.wang@mediatek.com>
Hello!
On Tuesday 20 April 2021 14:17:21 Jianjun Wang wrote:
> +static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
> +{
> + int i;
> + u32 val;
> +
> + for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
> + struct mtk_msi_set *msi_set = &port->msi_sets[i];
> +
> + msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
> + i * PCIE_MSI_SET_OFFSET;
> + msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
> + i * PCIE_MSI_SET_OFFSET;
> +
> + /* Configure the MSI capture address */
> + writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
> + writel_relaxed(upper_32_bits(msi_set->msg_addr),
> + port->base + PCIE_MSI_SET_ADDR_HI_BASE +
> + i * PCIE_MSI_SET_ADDR_HI_OFFSET);
This looks like as setting MSI doorbell address to MSI doorbell address.
> +static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> + struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
> + struct mtk_pcie_port *port = data->domain->host_data;
> + unsigned long hwirq;
> +
> + hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
> +
> + msg->address_hi = upper_32_bits(msi_set->msg_addr);
> + msg->address_lo = lower_32_bits(msi_set->msg_addr);
> + msg->data = hwirq;
> + dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
> + hwirq, msg->address_hi, msg->address_lo, msg->data);
... which is later used in compose_msi_msg().
Marc in some other patches for other pci controller drivers changed this
address to just main "port" structure. It simplified implementations and
also avoided need to declare additional member "msg_addr".
Marc, would it be possible to simplify it also for this driver and just
set msg_addr to virt_to_phys(port)?
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next prev parent reply other threads:[~2021-04-20 9:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-20 6:17 [PATCH v10 0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-04-20 9:44 ` Pali Rohár [this message]
2021-04-20 11:01 ` Marc Zyngier
2021-04-20 11:08 ` Pali Rohár
2021-04-20 6:17 ` [PATCH v10 6/7] PCI: mediatek-gen3: Add system PM support Jianjun Wang
2021-04-20 6:17 ` [PATCH v10 7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang
2021-04-20 9:12 ` [PATCH v10 0/7] PCI: mediatek: Add new generation controller support Lorenzo Pieralisi
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