Re: [PATCH 1/4] coresight: tmc-etr: Advance buffer pointer in sync buffer.

Leo Yan
2021-04-28T02:36:22Z

On Tue, Apr 27, 2021 at 11:00:51AM +0100, Suzuki Kuruppassery Poulose wrote:

[...]

> To make it more clear:
>
> CPU0: AUX RB (perf_output_handle_0) -> etr_perf0 -> +---------+
> CPU1: AUX RB (perf_output_handle_1) -> etr_perf1 -> |etr_buf0 |
> CPU2: AUX RB (perf_output_handle_2) -> etr_perf2 -> | |
> CPU3: AUX RB (perf_output_handle_3) -> etr_perf3 -> +---------+

Thanks for the clarification.

> > Simply to say, there have two layers for controlling ring buffer, one
> > layer is for perf AUX ring buffer, it mainly uses the structure
> > perf_output_handle to manage the ring buffer. And in the ETR driver,
> > it uses structure etr_perf to manage the header pointer for copying
> > data into ETR buffer (tagged as "etr_buf").
> >
> > ETR buffer is the single one, but the structures "perf_output_handle"
> > and "etr_perf" are per CPU. We have multiple copies for the headers and
>
> minor Correction, they are "per-event" to be precise. And there are events
> per-CPU in a system wide mode or task mode (but not per-thread mode). So,
> you are correct
>
> > tails to manage a single buffer, but the problem is these multiple
> > copies have not been synced with each other.
> >
> > > 2) Even more problematic is where we copy the AUX buffer content to.
> > > As mentioned above, we don't know which handle is going to be the last
> > > one to consume and we have a "etr_perf->head" that came from one of the
> > > handles and the "pages" that came from the first handle which created a
> > > etr_perf buffer. In sync_perf_buffer() we copy the hardware buffers to
> > > the "pages" (say of handle_0) with "etr_perf->head" (which could be from
> > > any other handle, say handle_2) and then we could return the number of bytes
> > > copied, which then is used to update the last handle (could be say
> > > handle_3), where there is no actual data copied.
>
> This is not valid and am relieved that the driver is correct. The assumption
> that there is only one etr_perf per ETR is incorrect as
> pictured above.

Yeah, etr_perf is per event wise.

> > > To fix all of these issues, we must
> > > 1) Stop using etr_perf->head, and instead use the handle->head where we are
> > > called update_buffer on.
> > >
> > > 2) Keep track of the "pages" that belong to a given "handle" and then use
> > > those pages to copy the data to the current handle we are called to update
> > > the buffer on.
> >
> > The "pages" are only allocated once, even they are attached to multiple
> > handles. I think the right way is to use the single structure
>
> I assume you mean the pages in the etr_buf and not etr_perf right ?

Yes.

> > "etr_perf" and single "perf_output_handle" to manage the "pages", IOW,
> > if there have single buffer, then we just use one copy of header and
> > tail to manage it.
>
> I think this is not needed and the way we do things are fine and the patch
> as such looks correct to me.
>
> The perf_output_handle is per-event and nothing that we can combine with.
> etr_perf captures what the "ouput_handle" stands for and is something
> necessary for syncing the buffer.

Correct myself for one thing. At beginning I wrongly understood the AUX
buffer is only allocated once but mapped into VMA for multiple times for all
events, but this is wrong. In the file kernel/events/ring_buffer.c,
function rb_alloc_aux() clearly shows the AUX ring buffer is allocated
for every event. So the buffer management is as below:

+---------+
CPU0: | AUX RB0 | (perf_output_handle_0) -> etr_perf0 -> +---------+
+---------+ | |
CPU1: | AUX RB1 | (perf_output_handle_1) -> etr_perf1 -> |etr_buf0 |
+---------+ | |
CPU2: | AUX RB2 | (perf_output_handle_2) -> etr_perf2 -> | |
+---------+ | |
CPU3: | AUX RB3 | (perf_output_handle_3) -> etr_perf3 -> +---------+
+---------+ |
^---------------------------------------------------/
tmc_etr_sync_perf_buffer()

> Now coming back to this patch, I understand that the sync_perf could be
> called with the polling patches multiple times. But don't we do a
> perf_output_handle_end() each of the time we wake up ? (I haven't looked
> at the later patches yet).

Here "we" means the polling's work (or we can say the polling thread).
From my understanding for the patch of implementation the polling, it
adds the delayed work on work queue periodically, every time the work
resets the ETR and sync the trace data from etr_buf0 to AUX ring
buffer. The target AUX ring buffer is fixed, it should be the first
registered AUX ring buffer when launch the session.

So the flow is:

etr_perf_polling_worker()
sink_ops(sink)->update_buffer()
tmc_etr_sync_perf_buffer() -> Update 'etr_perf->head'
tmc_etr_reset
perf_aux_output_end(handle, size) -> Update AUX ring buffer head
and notify the perf tool
perf_aux_output_begin() -> Prepare for next recording

> I would expect:
>
> perf_aux_output_begin() -> update the etr_perf-> head
>
> when we sync the buffer, we do :
>
> Poll-> sync_buffer-> perf_aux_output_end() and perf_aux_output_begin() ->
> update etr_perf->head.

I understand your meaning, essentially "etr_perf->head" should keep
up the latest value of the AUX ring buffer's head. So I think below
change is what you are proposing:

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 8e8596dc75fa..daeeda00236e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1567,6 +1567,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
/* Insert barrier packets at the beginning, if there was an overflow */
if (lost)
tmc_etr_buf_insert_barrier_packet(etr_buf, offset);
+ etr_perf->head = handle->head;
tmc_etr_sync_perf_buffer(etr_perf, offset, size);

/*

Thanks,
Leo