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Mon, 26 Apr 2021 02:01:03 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id C043B611BD; Mon, 26 Apr 2021 02:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1619402458; bh=PBSZMZjXTRgQdMRY26riL1Zlj5dFth8iLcEaBII3B6o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=PNhgDcVUKQV/MFAnK1G6q23GOj5edc5p7Mzuf2LEiWKMZCMgpHSolQEaz1DadrSIB 2GIT0uB6kHZRXaYFfEFpIbAzyvUarmXsMwAit7hVjxt0wBmdHe7BE4d7JEu3xTH5Fy xSwme9kTUfhS6/8gg+1X/xd/WZGiF+dtyg/Yt/yb03wLODalkFlU7HgkI7uJZDMWmb hV4dV9k1nD0thVjEgmHnS8kryLJzVkpN8D7REuT7PJGg1b2LAQeFvWaNctJzdxKRUX la0LS0H/+x2rg4o2iMzKengW0DYnYGFBJZCTcqWmbg+rwd96Anl3ZDgdMBFb0zZGCf P9CTF3zV3tdpw== Date: Mon, 26 Apr 2021 10:00:54 +0800 From: Shawn Guo To: Richard Zhu Cc: "l.stach@pengutronix.de" , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: Re: [PATCH] arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy Message-ID: <20210426020053.GE27585@dragon> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210425_190101_746625_E9C1AA30 X-CRM114-Status: GOOD ( 21.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Apr 26, 2021 at 01:28:34AM +0000, Richard Zhu wrote: > > -----Original Message----- > > > Subject: Re: [PATCH] arm64: dts: imx8mq-evk: add one regulator used > > to power up pcie phy > > On Mon, Mar 29, 2021 at 04:06:03PM +0800, Richard Zhu wrote: > > > Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. > > > In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data > > > sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, > > > the VREG_BYPASS bits of GPR registers should be cleared from default > > > value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be > > > turned on. > > > > > > Signed-off-by: Richard Zhu > > > Reviewed-by: Lucas Stach > > > --- > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > index 85b045253a0e..4d2035e3dd7c 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > @@ -318,6 +318,7 @@ > > > <&clk IMX8MQ_CLK_PCIE1_PHY>, > > > <&pcie0_refclk>; > > > clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > > > + vph-supply = <&vgen5_reg>; > > > > Hmm, I do not see this in the bindings doc. > [Richard Zhu] Hi Shawn: > The binding document changes are going to PCI tree by the following patch. > > https://patchwork.kernel.org/project/linux-pci/patch/1617091701-6444-2-git-send-email-hongxing.zhu@nxp.com/ Ah, okay, ping me when the series is applied to PCI tree. Shawn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel