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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id b64sm215922oii.12.2021.04.30.15.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 15:14:43 -0700 (PDT) Received: (nullmailer pid 4001411 invoked by uid 1000); Fri, 30 Apr 2021 22:14:42 -0000 Date: Fri, 30 Apr 2021 17:14:42 -0500 From: Rob Herring To: Ezequiel Garcia Cc: Benjamin Gaignard , joro@8bytes.org, will@kernel.org, heiko@sntech.de, xxm@rock-chips.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Kever Yang Subject: Re: [PATCH v2 1/4] dt-bindings: iommu: rockchip: Convert IOMMU to DT schema Message-ID: <20210430221442.GA3970483@robh.at.kernel.org> References: <20210422141602.350746-1-benjamin.gaignard@collabora.com> <20210422141602.350746-2-benjamin.gaignard@collabora.com> <7557bc8aaaa1924ad39676b32ba6a3f6474a3722.camel@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7557bc8aaaa1924ad39676b32ba6a3f6474a3722.camel@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210430_151445_479377_34075E67 X-CRM114-Status: GOOD ( 30.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 22, 2021 at 02:16:53PM -0300, Ezequiel Garcia wrote: > (Adding Kever) > = > Hi Benjamin, > = > Thanks a lot for working on this, it looks amazing. Together with the gre= at work > that Rockchip is doing, it seems RK3566/RK3568 will have decent support v= ery soon. > = > One comment here: > = > On Thu, 2021-04-22 at 16:15 +0200, Benjamin Gaignard wrote: > > Convert Rockchip IOMMU to DT schema > > = > > Signed-off-by: Benjamin Gaignard > > --- > > version 2: > > =A0- Change maintainer > > =A0- Change reg maxItems > > =A0- Change interrupt maxItems > > = > > =A0.../bindings/iommu/rockchip,iommu.txt=A0=A0=A0=A0=A0=A0=A0=A0 | 38 -= -------- > > =A0.../bindings/iommu/rockchip,iommu.yaml=A0=A0=A0=A0=A0=A0=A0 | 79 +++= ++++++++++++++++ > > =A02 files changed, 79 insertions(+), 38 deletions(-) > > =A0delete mode 100644 Documentation/devicetree/bindings/iommu/rockchip,= iommu.txt > > =A0create mode 100644 Documentation/devicetree/bindings/iommu/rockchip,= iommu.yaml > > = > > diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt= b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt > > deleted file mode 100644 > > index 6ecefea1c6f9..000000000000 > > --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt > > +++ /dev/null > > @@ -1,38 +0,0 @@ > > -Rockchip IOMMU > > -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > - > > -A Rockchip DRM iommu translates io virtual addresses to physical addre= sses for > > -its master device.=A0 Each slave device is bound to a single master de= vice, and > > -shares its clocks, power domain and irq. > > - > > -Required properties: > > -- compatible=A0=A0=A0=A0=A0 : Should be "rockchip,iommu" > > -- reg=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 : Address space for the conf= iguration registers > > -- interrupts=A0=A0=A0=A0=A0 : Interrupt specifier for the IOMMU instan= ce > > -- interrupt-names : Interrupt name for the IOMMU instance > > -- #iommu-cells=A0=A0=A0 : Should be <0>.=A0 This indicates the iommu i= s a > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "single-mast= er" device, and needs no additional information > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 to associate= with its master device.=A0 See: > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Documentatio= n/devicetree/bindings/iommu/iommu.txt > > -- clocks=A0=A0=A0=A0=A0=A0=A0=A0=A0 : A list of clocks required for th= e IOMMU to be accessible by > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 the host CPU. > > -- clock-names=A0=A0=A0=A0 : Should contain the following: > > -=A0=A0=A0=A0=A0=A0=A0"iface" - Main peripheral bus clock (PCLK/HCL) (r= equired) > > -=A0=A0=A0=A0=A0=A0=A0"aclk"=A0 - AXI bus clock (required) > > - > > -Optional properties: > > -- rockchip,disable-mmu-reset : Don't use the mmu reset operation. > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 Some mmu instances may produce unexpected results > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 when the reset operation is used. > > - > > -Example: > > - > > -=A0=A0=A0=A0=A0=A0=A0vopl_mmu: iommu@ff940300 { > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0compatible =3D "rockchip,= iommu"; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0reg =3D <0xff940300 0x100= >; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0interrupts =3D ; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0interrupt-names =3D "vopl= _mmu"; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0clocks =3D <&cru ACLK_VOP= 1>, <&cru HCLK_VOP1>; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0clock-names =3D "aclk", "= iface"; > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0#iommu-cells =3D <0>; > > -=A0=A0=A0=A0=A0=A0=A0}; > > diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yam= l b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml > > new file mode 100644 > > index 000000000000..0db208cf724a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml > > @@ -0,0 +1,79 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip IOMMU > > + > > +maintainers: > > +=A0 - Heiko Stuebner > > + > > +description: |+ > > +=A0 A Rockchip DRM iommu translates io virtual addresses to physical a= ddresses for > > +=A0 its master device. Each slave device is bound to a single master d= evice and > > +=A0 shares its clocks, power domain and irq. > > + > > +=A0 For information on assigning IOMMU controller to its peripheral de= vices, > > +=A0 see generic IOMMU bindings. > > + > > +properties: > > +=A0 compatible: > > +=A0=A0=A0 const: rockchip,iommu > > + > > +=A0 reg: > > +=A0=A0=A0 minItems: 1 > > +=A0=A0=A0 maxItems: 2 > > + > > +=A0 interrupts: > > +=A0=A0=A0 minItems: 1 > > +=A0=A0=A0 maxItems: 2 > > + > > +=A0 interrupt-names: > > +=A0=A0=A0 minItems: 1 > > +=A0=A0=A0 maxItems: 2 > > + > = > AFAICS, the driver supports handling multiple MMUs, and there's one reg a= nd > interrupt cell for each MMU. IOW, there's no requirement that maxItems is= 2. > = > Is there any way we can describe that? Or maybe just allow a bigger maxim= um? With #iommu-cells =3D=3D 0, how would one distinguish which IOMMU is = associated with a device? IOW, is more that 1 really usable? If you need more just pick a maxItems value that's either the most seen = or 'should be enough'TM. If the entries are just multiple instances of = the same thing, please note that here. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel