From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5F34C43460 for ; Tue, 11 May 2021 15:25:11 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6FD461400 for ; Tue, 11 May 2021 15:25:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6FD461400 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=e3OkVs/fgnjeoBc2SbDem0qw0mAL84x74bjXF4XXw5M=; b=mP8/q3lrA8FVpluLKGWKFrPCr prrFDVwMj2n2qVOSZkVGfxhfE+Iw/bxXyBSs0C/S2KfnFiiF5LKwjbJkAxBYqCClQ7CgeV2D2VPms /1JZQnQ/5oW7rhCI4dyZciFmcUUCTzZdPWQG1schEZUC0LbUt8ZI14tz6xTdG8IuQ9BBZnCmCbsvu GAV9CfCpB3wm+ra0UDMCCs25UBvbvAfpQTQpQpokzhGwIaD/x6yryuKQ7m/8Qse+lAyvCzn3+fvDA 9dPNi//IYzXcQEAcvbwuG8K/Im3XuE3vKVxeMu7KwJza3gsZbb2LXC9z+XybKAI6TQ5tAaLkQXvYi /6htl1gPA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgUE3-000awo-Kx; Tue, 11 May 2021 15:23:11 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgUE0-000awK-DW for linux-arm-kernel@desiato.infradead.org; Tue, 11 May 2021 15:23:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Fq0fA8LZ6Ftx6/AoDBOmbbEZMi7WNsWyXUhrPvYcLJQ=; b=fqr8pGT07+16+JwFqN2HDKD7ZD U66pREWg9dQVjj/jH1FJfBqgcl95yGdWQyfQbsxowYBEZeStli+UNWHfyvaIjT92zqP1NU4yO6a76 dXs2Elji6RFPK6PfQOgg74ocNm7AEimDYz4mb89ZKiu+bDELP3iAKqhrCTBRNrecF7JeDfCNHP9Sf bDAtsX27TIiXx4WDEuNkxMlyLvuOd1BUxPIV11v2IE2Ziw06PbMEpJmWZGpFvLbyDXsk7ZFPS1kkJ CLlwtpnpnOraNGMy6ajypAxaIrLGrU/lMdcSrN5RIWQfxoB/x6qCWtSicOUs06jn20j4E81rfUHgM 5syAFKrg==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgUDw-009iPp-WA for linux-arm-kernel@lists.infradead.org; Tue, 11 May 2021 15:23:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 042D7D6E; Tue, 11 May 2021 08:23:00 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.29.91]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B6A623F718; Tue, 11 May 2021 08:22:57 -0700 (PDT) Date: Tue, 11 May 2021 16:22:55 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com Subject: Re: [PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range Message-ID: <20210511152255.GD8933@C02TD0UTHF1T.local> References: <20210511144252.3779113-1-tabba@google.com> <20210511144252.3779113-2-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210511144252.3779113-2-tabba@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210511_082305_187232_F6799084 X-CRM114-Status: GOOD ( 24.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Fuad, On Tue, May 11, 2021 at 03:42:40PM +0100, Fuad Tabba wrote: > __flush_icache_range works on the kernel linear map, and doesn't > need uaccess. The existing code is a side-effect of its current > implementation with __flush_cache_user_range fallthrough. > > Instead of fallthrough to share the code, use a common macro for > the two where the caller can specify whether user-space access is > needed. FWIW, I agree that we should fix __flush_icache_range to not map fiddle with uaccess, and that we should split these. > No functional change intended. There is a performance change here, since the existing `__flush_cache_user_range` takes IDC and DIC into account, whereas `invalidate_icache_by_line` does not. There's also an existing oversight where `__flush_cache_user_range` takes ARM64_WORKAROUND_CLEAN_CACHE into account, but `invalidate_icache_by_line` does not. I think that's a bug that we should fix first, so that we can backport something to stable. Arguably similar is true in `swsusp_arch_suspend_exit`, but for that we could add a comment and always use `DC CIVAC`. Thanks, Mark. > Reported-by: Catalin Marinas > Reported-by: Will Deacon > Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/ > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/assembler.h | 13 ++++-- > arch/arm64/mm/cache.S | 64 +++++++++++++++++++++--------- > 2 files changed, 54 insertions(+), 23 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index 8418c1bd8f04..6ff7a3a3b238 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -426,16 +426,21 @@ alternative_endif > * Macro to perform an instruction cache maintenance for the interval > * [start, end) > * > - * start, end: virtual addresses describing the region > - * label: A label to branch to on user fault. > - * Corrupts: tmp1, tmp2 > + * start, end: virtual addresses describing the region > + * needs_uaccess: might access user space memory > + * label: label to branch to on user fault (if needs_uaccess) > + * Corrupts: tmp1, tmp2 > */ > - .macro invalidate_icache_by_line start, end, tmp1, tmp2, label > + .macro invalidate_icache_by_line start, end, tmp1, tmp2, needs_uaccess, label > icache_line_size \tmp1, \tmp2 > sub \tmp2, \tmp1, #1 > bic \tmp2, \start, \tmp2 > 9997: > + .if \needs_uaccess > USER(\label, ic ivau, \tmp2) // invalidate I line PoU > + .else > + ic ivau, \tmp2 > + .endif > add \tmp2, \tmp2, \tmp1 > cmp \tmp2, \end > b.lo 9997b > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 2d881f34dd9d..092f73acdf9a 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -15,30 +15,20 @@ > #include > > /* > - * flush_icache_range(start,end) > + * __flush_cache_range(start,end) [needs_uaccess] > * > * Ensure that the I and D caches are coherent within specified region. > * This is typically used when code has been written to a memory region, > * and will be executed. > * > - * - start - virtual start address of region > - * - end - virtual end address of region > + * - start - virtual start address of region > + * - end - virtual end address of region > + * - needs_uaccess - (macro parameter) might access user space memory > */ > -SYM_FUNC_START(__flush_icache_range) > - /* FALLTHROUGH */ > - > -/* > - * __flush_cache_user_range(start,end) > - * > - * Ensure that the I and D caches are coherent within specified region. > - * This is typically used when code has been written to a memory region, > - * and will be executed. > - * > - * - start - virtual start address of region > - * - end - virtual end address of region > - */ > -SYM_FUNC_START(__flush_cache_user_range) > +.macro __flush_cache_range, needs_uaccess > + .if \needs_uaccess > uaccess_ttbr0_enable x2, x3, x4 > + .endif > alternative_if ARM64_HAS_CACHE_IDC > dsb ishst > b 7f > @@ -47,7 +37,11 @@ alternative_else_nop_endif > sub x3, x2, #1 > bic x4, x0, x3 > 1: > + .if \needs_uaccess > user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE > + .else > +alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE > + .endif > add x4, x4, x2 > cmp x4, x1 > b.lo 1b > @@ -58,15 +52,47 @@ alternative_if ARM64_HAS_CACHE_DIC > isb > b 8f > alternative_else_nop_endif > - invalidate_icache_by_line x0, x1, x2, x3, 9f > + invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f > 8: mov x0, #0 > 1: > + .if \needs_uaccess > uaccess_ttbr0_disable x1, x2 > + .endif > ret > + > + .if \needs_uaccess > 9: > mov x0, #-EFAULT > b 1b > + .endif > +.endm > + > +/* > + * flush_icache_range(start,end) > + * > + * Ensure that the I and D caches are coherent within specified region. > + * This is typically used when code has been written to a memory region, > + * and will be executed. > + * > + * - start - virtual start address of region > + * - end - virtual end address of region > + */ > +SYM_FUNC_START(__flush_icache_range) > + __flush_cache_range needs_uaccess=0 > SYM_FUNC_END(__flush_icache_range) > + > +/* > + * __flush_cache_user_range(start,end) > + * > + * Ensure that the I and D caches are coherent within specified region. > + * This is typically used when code has been written to a memory region, > + * and will be executed. > + * > + * - start - virtual start address of region > + * - end - virtual end address of region > + */ > +SYM_FUNC_START(__flush_cache_user_range) > + __flush_cache_range needs_uaccess=1 > SYM_FUNC_END(__flush_cache_user_range) > > /* > @@ -86,7 +112,7 @@ alternative_else_nop_endif > > uaccess_ttbr0_enable x2, x3, x4 > > - invalidate_icache_by_line x0, x1, x2, x3, 2f > + invalidate_icache_by_line x0, x1, x2, x3, 1, 2f > mov x0, xzr > 1: > uaccess_ttbr0_disable x1, x2 > -- > 2.31.1.607.g51e8a6a459-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel