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Wed, 12 May 2021 13:34:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0BDCF6D; Wed, 12 May 2021 06:33:55 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.72.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F20023F718; Wed, 12 May 2021 06:33:53 -0700 (PDT) Date: Wed, 12 May 2021 14:33:51 +0100 From: Mark Rutland To: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Suzuki K Poulose Subject: Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Message-ID: <20210512133351.GD93815@C02TD0UTHF1T.local> References: <20210511182322.3830-1-catalin.marinas@arm.com> <20210511182322.3830-3-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210511182322.3830-3-catalin.marinas@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210512_063400_636384_6C2722D0 X-CRM114-Status: GOOD ( 20.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 11, 2021 at 07:23:22PM +0100, Catalin Marinas wrote: > The GMID_EL1.BS field determines the number of tags accessed by the > LDGM/STGM instructions (EL1 and up), used by the kernel for copying or > zeroing page tags. > > Taint the kernel if GMID_EL1.BS differs between CPUs. > > Signed-off-by: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: Suzuki K Poulose Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > 3 files changed, 19 insertions(+) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index fe5a8499ddc2..9088e72c7cf6 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -20,6 +20,7 @@ struct cpuinfo_arm64 { > u64 reg_dczid; > u64 reg_midr; > u64 reg_revidr; > + u64 reg_gmid; > > u64 reg_id_aa64dfr0; > u64 reg_id_aa64dfr1; > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index ca66a61bb396..3b9089ca52dc 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -401,6 +401,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_gmid[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), > + ARM64_FTR_END, > +}; > + > static const struct arm64_ftr_bits ftr_id_isar0[] = { > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), > @@ -618,6 +623,9 @@ static const struct __ftr_reg_entry { > /* Op1 = 0, CRn = 1, CRm = 2 */ > ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), > > + /* Op1 = 1, CRn = 0, CRm = 0 */ > + ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), > + > /* Op1 = 3, CRn = 0, CRm = 0 */ > { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, > ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), > @@ -872,6 +880,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) > init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); > init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); > init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); > + init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); > init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); > init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); > init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); > @@ -1082,6 +1091,14 @@ void update_cpu_features(int cpu, > taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, > info->reg_dczid, boot->reg_dczid); > > + /* > + * The kernel uses the LDGM/STGM instructions and the number of tags > + * they read/write depends on the GMID_EL1.BS field. Check that the > + * value is the same on all CPUs. > + */ > + taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, > + info->reg_gmid, boot->reg_gmid); > + > /* If different, timekeeping will be broken (especially with KVM) */ > taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, > info->reg_cntfrq, boot->reg_cntfrq); > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 4bea701117d4..cd9f2d51285b 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -359,6 +359,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) > info->reg_dczid = read_cpuid(DCZID_EL0); > info->reg_midr = read_cpuid_id(); > info->reg_revidr = read_cpuid(REVIDR_EL1); > + info->reg_gmid = read_cpuid(GMID_EL1); > > info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); > info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel