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Fri, 14 May 2021 11:03:26 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7C76C611CA; Fri, 14 May 2021 11:03:24 +0000 (UTC) Date: Fri, 14 May 2021 12:03:22 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Dave Martin , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors Message-ID: <20210514110321.GE855@arm.com> References: <20210512151131.27877-1-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210512151131.27877-1-broonie@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210514_040325_736970_8A9E40CD X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 12, 2021 at 04:11:28PM +0100, Mark Brown wrote: > This series is a combination of factoring out some duplicated code and a > very minor optimisation to the performance of handling converting FPSIMD > state to SVE in the live registers for 128 bit SVE vectors. > > v3: > - Tweak comment. > v2: > - Combine P and FFR flushing into a single macro. > > Mark Brown (3): > arm64/sve: Split _sve_flush macro into separate Z and predicate > flushes > arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state() > arm64/sve: Skip flushing Z registers with 128 bit vectors I acked v2, hadn't noticed v3 was out. So here it is again: Acked-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel