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Tue, 18 May 2021 16:00:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59FF36D; Tue, 18 May 2021 09:00:11 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.6.226]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 881343F73B; Tue, 18 May 2021 09:00:09 -0700 (PDT) Date: Tue, 18 May 2021 17:00:07 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v2 05/16] arm64: Remove uaccess toggle from __flush_cache_range macro Message-ID: <20210518160007.GM82842@C02TD0UTHF1T.local> References: <20210517075124.152151-1-tabba@google.com> <20210517075124.152151-6-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210517075124.152151-6-tabba@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_090014_691772_1C1CF11E X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 17, 2021 at 08:51:13AM +0100, Fuad Tabba wrote: > The uaccess toggle isn't part of the cache maintenance operation. > Move it directly to where it's needed. > > No functional change intended. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/mm/cache.S | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 6babaaf34f17..d74b20cd6449 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -26,9 +26,6 @@ > * - needs_uaccess - (macro parameter) might access user space memory > */ > .macro __flush_cache_range, needs_uaccess > - .if \needs_uaccess > - uaccess_ttbr0_enable x2, x3, x4 > - .endif > alternative_if ARM64_HAS_CACHE_IDC > dsb ishst > b 7f > @@ -55,9 +52,6 @@ alternative_else_nop_endif > invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f > 8: mov x0, #0 > 1: > - .if \needs_uaccess > - uaccess_ttbr0_disable x1, x2 > - .endif > ret > > .if \needs_uaccess > @@ -92,7 +86,9 @@ SYM_FUNC_END(__flush_icache_range) > * - end - virtual end address of region > */ > SYM_FUNC_START(__flush_cache_user_range) > + uaccess_ttbr0_enable x2, x3, x4 > __flush_cache_range needs_uaccess=1 > + uaccess_ttbr0_disable x1, x2 > SYM_FUNC_END(__flush_cache_user_range) The RET is still in the __flush_cache_range macro, so I don't think we'll ever execute the uaccess_ttbr0_disable step here. Mark. > > /* > -- > 2.31.1.751.gd2f1c929bd-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel