From: Shawn Guo <shawnguo@kernel.org>
To: Kornel Duleba <mindal@semihalf.com>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, leoyang.li@nxp.com,
robh+dt@kernel.org, mw@semihalf.com, tn@semihalf.com,
upstream@semihalf.com
Subject: Re: [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
Date: Sat, 22 May 2021 20:27:20 +0800 [thread overview]
Message-ID: <20210522122719.GA3425@dragon> (raw)
In-Reply-To: <20210407123438.224551-1-mindal@semihalf.com>
On Wed, Apr 07, 2021 at 02:34:38PM +0200, Kornel Duleba wrote:
> Currently all PCIE windows point to bus address 0x0, which does not match
> the values obtained from hardware during EA.
> Replace those values with CPU addresses, since in reality we
> have a 1:1 mapping between the two.
>
> Signed-off-by: Kornel Duleba <mindal@semihalf.com>
Applied, thanks.
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prev parent reply other threads:[~2021-05-22 12:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 12:34 [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges Kornel Duleba
2021-04-16 11:36 ` Kornel Dulęba
2021-05-11 3:06 ` Shawn Guo
2021-05-11 9:48 ` Claudiu Manoil
2021-05-13 2:12 ` Shawn Guo
2021-05-13 14:19 ` Vladimir Oltean
2021-05-13 17:54 ` Marcin Wojtas
2021-05-13 18:31 ` Vladimir Oltean
2021-05-14 8:25 ` Kornel Dulęba
2021-05-19 14:28 ` Kornel Dulęba
2021-05-22 12:27 ` Shawn Guo [this message]
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