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Sun, 23 May 2021 02:45:34 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6B6B661182; Sun, 23 May 2021 02:45:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621737932; bh=Y6WLoSe/Pi0Ngn3JuKsbJYXY4hlha4IGsjsiVXRrjqY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qNXckVruhRgBKhOy2HvotC7gH9Nhh62qfTE88k78hc0a3cM16ug5156ljMi7PsMBO 6QqkQkD2JimPO15xiU56rnSYr4UTLB9KQaB/li0408T8dovmKBgs5EluFPQHr08n8H pcDxjuZsj4aoUlwnlxEnjNQ1m9N8p39mOsNfl0QTTsCmkLyYaKt2AxHfMbxlA6OxEw Fjm+getbptf0CxEHGSnRfKHOPaHFBH1mleREoJ35pi6TXyGcMozo9oBPcDMNKwS6dk j846ZfBdpkOkcsr/QsINgz7A4D4Zl/7QLs7xUUVIF2zs7Fbx62H/fhRPt3JkWdbJdo 56Y3Lfq7GB3CQ== Date: Sun, 23 May 2021 10:45:28 +0800 From: Shawn Guo To: Lucas Stach Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Fabio Estevam , kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: Re: [PATCH] arm64: dts: imx8mq: assign PCIe clocks Message-ID: <20210523024520.GN8194@dragon> References: <20210507221213.166092-1-l.stach@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210507221213.166092-1-l.stach@pengutronix.de> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210522_194533_625042_7C53A18A X-CRM114-Status: GOOD ( 12.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, May 08, 2021 at 12:12:13AM +0200, Lucas Stach wrote: > This fixes multiple issues with the current non-existent PCIe clock setup: > > The controller can run at up to 250MHz, so use a parent that provides this > clock. > > The PHY needs an exact 100MHz reference clock to function if the PCIe > refclock is not fed in via the refclock pads. While this mode is not > supported (yet) in the driver it doesn't hurt to make sure we are > providing a clock with the right rate. > > The AUX clock is specified to have a maximum clock rate of 10MHz. So > the current setup, which drives it straight from the 25MHz oscillator is > actually overclocking the AUX input. > > Signed-off-by: Lucas Stach Applied, thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel