From: Bjorn Helgaas <helgaas@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: "Peter Geis" <pgwipeout@gmail.com>,
"Punit Agrawal" <punitagrawal@gmail.com>,
"Robin Murphy" <robin.murphy@arm.com>,
"Alexandru Elisei" <alexandru.elisei@arm.com>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip@lists.infradead.org>,
arm-mail-list <linux-arm-kernel@lists.infradead.org>,
"Heiko Stuebner" <heiko.stuebner@theobroma-systems.com>,
"Leonardo Bras" <leobras.c@gmail.com>,
"Rob Herring" <robh@kernel.org>, PCI <linux-pci@vger.kernel.org>,
"Christian König" <ckoenig.leichtzumerken@gmail.com>
Subject: Re: [BUG] rockpro64: PCI BAR reassignment broken by commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses")
Date: Tue, 25 May 2021 14:15:56 -0500 [thread overview]
Message-ID: <20210525191556.GA1220872@bjorn-Precision-5520> (raw)
In-Reply-To: <CAMj1kXEBePfKDOc6eo9yjZPnVeFimX-zxR+R3As+2pP9XnZkuQ@mail.gmail.com>
On Tue, May 25, 2021 at 05:54:56PM +0200, Ard Biesheuvel wrote:
> On Tue, 25 May 2021 at 17:34, Peter Geis <pgwipeout@gmail.com> wrote:
> > > > >> > On 2021-05-18 10:09, Alexandru Elisei wrote:
> > > > >> >> [..]
> > > > >> >> [ 0.305183] rockchip-pcie f8000000.pcie: host bridge /pcie@f8000000 ranges:
> > > > >> >> [ 0.305248] rockchip-pcie f8000000.pcie: MEM 0x00fa000000..0x00fbdfffff -> 0x00fa000000
> > > > >> >> [ 0.305285] rockchip-pcie f8000000.pcie: IO 0x00fbe00000..0x00fbefffff -> 0x00fbe00000
> > > > >> >> [ 0.373705] rockchip-pcie f8000000.pcie: PCI host bridge to bus 0000:00
> > > > >> >> [ 0.373730] pci_bus 0000:00: root bus resource [bus 00-1f]
> > > > >> >> [ 0.373751] pci_bus 0000:00: root bus resource [mem 0xfa000000-0xfbdfffff 64bit]
> > > > >> >> [ 0.373777] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff] (bus address [0xfbe00000-0xfbefffff])
> ... For some reason, lspci translates the BAR values to CPU
> addresses, but the PCI side addresses are within 32-bits.
lspci shows BARs as CPU physical addresses by default. These are the
same addresses you would see in pdev->resource[n] and the same as BAR
values you would see in dmesg.
A 64-bit CPU physical address can certainly be translated by the host
bridge to a 32-bit PCI address. But that's not happening here because
this host bridge applies no translation (CPU physical 0xfa000000 maps
to bus address 0xfa000000).
"lspci -b" shows the PCI bus addresses.
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next prev parent reply other threads:[~2021-05-25 19:35 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-18 9:09 [BUG] rockpro64: PCI BAR reassignment broken by commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses") Alexandru Elisei
2021-05-19 6:28 ` Qu Wenruo
2021-05-19 7:05 ` Qu Wenruo
2021-05-19 9:20 ` Alexandru Elisei
2021-05-19 11:16 ` Qu Wenruo
2021-05-19 11:27 ` Robin Murphy
2021-05-19 13:17 ` Peter Geis
2021-05-23 11:03 ` Punit Agrawal
2021-05-23 12:10 ` Ard Biesheuvel
2021-05-25 13:42 ` Punit Agrawal
2021-05-25 13:54 ` Ard Biesheuvel
2021-05-25 15:34 ` Peter Geis
2021-05-25 15:54 ` Ard Biesheuvel
2021-05-25 16:23 ` Peter Geis
2021-05-25 16:44 ` Ard Biesheuvel
2021-05-25 17:01 ` Peter Geis
2021-05-25 17:18 ` Ard Biesheuvel
2021-05-25 17:37 ` Peter Geis
2021-05-26 13:55 ` Christian König
2021-05-26 14:15 ` Ard Biesheuvel
2021-05-25 17:25 ` Robin Murphy
2021-05-25 17:34 ` Peter Geis
2021-05-25 18:55 ` Robin Murphy
2021-05-25 19:15 ` Bjorn Helgaas [this message]
2021-05-25 19:43 ` Ard Biesheuvel
2021-05-25 20:03 ` Peter Geis
2021-05-26 14:18 ` Ard Biesheuvel
2021-05-25 16:59 ` Anand Moon
2021-05-25 17:14 ` Robin Murphy
2021-05-25 17:42 ` Peter Geis
2021-05-25 22:36 ` Punit Agrawal
2021-05-26 15:37 ` Rob Herring
2021-05-26 16:35 ` Ard Biesheuvel
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