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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:44672) by pandora.armlinux.org.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lon5j-0002nA-6s; Thu, 03 Jun 2021 14:08:55 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1lon5f-00027a-7e; Thu, 03 Jun 2021 14:08:51 +0100 Date: Thu, 3 Jun 2021 14:08:51 +0100 From: "Russell King (Oracle)" To: Michael Sit Wei Hong Cc: Jose.Abreu@synopsys.com, andrew@lunn.ch, hkallweit1@gmail.com, kuba@kernel.org, netdev@vger.kernel.org, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, davem@davemloft.net, mcoquelin.stm32@gmail.com, weifeng.voon@intel.com, boon.leong.ong@intel.com, tee.min.tan@intel.com, vee.khee.wong@linux.intel.com, vee.khee.wong@intel.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps speed for stmmac Message-ID: <20210603130851.GS30436@shell.armlinux.org.uk> References: <20210603115032.2470-1-michael.wei.hong.sit@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210603115032.2470-1-michael.wei.hong.sit@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210603_060913_926375_2B6C3CA9 X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote: > Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate > by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY > operates at a serial baud rate of 3.125 Gbps and the PCS data path and > GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz. > This is configured in the BIOS during boot up. The kernel driver is not able > access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to > determine the current 1G/2.5G mode is by reading a dedicated adhoc > register through mdio bus. How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops" series? Is there an inter-dependency between these, or a preferred order that they should be applied? Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel