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Thu, 03 Jun 2021 06:28:11 -0700 (PDT) Date: Thu, 3 Jun 2021 16:28:09 +0300 From: Vladimir Oltean To: "Russell King (Oracle)" Cc: Michael Sit Wei Hong , Jose.Abreu@synopsys.com, andrew@lunn.ch, hkallweit1@gmail.com, kuba@kernel.org, netdev@vger.kernel.org, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, davem@davemloft.net, mcoquelin.stm32@gmail.com, weifeng.voon@intel.com, boon.leong.ong@intel.com, tee.min.tan@intel.com, vee.khee.wong@linux.intel.com, vee.khee.wong@intel.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps speed for stmmac Message-ID: <20210603132809.2z3jhpuxaryaql6v@skbuf> References: <20210603115032.2470-1-michael.wei.hong.sit@intel.com> <20210603130851.GS30436@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210603130851.GS30436@shell.armlinux.org.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210603_062813_124065_05CAE38A X-CRM114-Status: GOOD ( 18.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Michael, On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle) wrote: > Hi, > > On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote: > > Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate > > by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY > > operates at a serial baud rate of 3.125 Gbps and the PCS data path and > > GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz. > > This is configured in the BIOS during boot up. The kernel driver is not able > > access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to > > determine the current 1G/2.5G mode is by reading a dedicated adhoc > > register through mdio bus. > > How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops" > series? Is there an inter-dependency between these, or a preferred order > that they should be applied? > > Thanks. My preferred order would be for my series to go in first, if possible, because I don't have hardware readily available to test, and VK already has tested my patches a few times until they reached a stable state. I went through your patches and I think rebasing on top of my phylink_pcs_ops conversion should be easy. Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel