From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD225C2B9F4 for ; Mon, 14 Jun 2021 17:57:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8779E61075 for ; Mon, 14 Jun 2021 17:57:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8779E61075 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gKLFr8gOqPPvO3ZEPtIJKCZFHNX6dSX0YaQEkBlbqL0=; b=44FC/NoftHTDnY 8Y6E2MRoY8JkEx3JZ1pNdnhz3nWfhzwkqg1wTHjQ8crtEgUpykRyRemIUMtHcw9JlaOAYfjL1hF/7 kvSbqafDgKemvgJYv5WnZ7PaYMbtkJDBiw05hFwAosc9IKNpDdFTrjEhGDvSKgSZvAaMHBiKvRKOp oSPnD+NcRbZfxSbCiXn3Pse6lqlI9Gs9Mc02FSgqip41OSKUypMruSkOCofcKCyJYaPVEXiGCsrwr 1HT4P/CF7CCTbYBKfzMP/kzodGxPW1rE84LSzv70kv+bY6ojW+z4dlMM1LZL9GW0re3TECSYzqddN WSpYxpZfrPognrStNocw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqor-00FYKr-Lb; Mon, 14 Jun 2021 17:56:17 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqon-00FYK0-6L for linux-arm-kernel@lists.infradead.org; Mon, 14 Jun 2021 17:56:14 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id EE3B061075; Mon, 14 Jun 2021 17:56:11 +0000 (UTC) Date: Mon, 14 Jun 2021 18:56:09 +0100 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Message-ID: <20210614175609.GI30667@arm.com> References: <20210611215101.1060663-1-pcc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210611215101.1060663-1-pcc@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210614_105613_274125_3B2C8193 X-CRM114-Status: GOOD ( 19.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 11, 2021 at 02:51:01PM -0700, Peter Collingbourne wrote: > diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst > index b540178a93f8..2fc145de6530 100644 > --- a/Documentation/arm64/memory-tagging-extension.rst > +++ b/Documentation/arm64/memory-tagging-extension.rst > @@ -120,6 +120,25 @@ in the ``PR_MTE_TAG_MASK`` bit-field. > interface provides an include mask. An include mask of ``0`` (exclusion > mask ``0xffff``) results in the CPU always generating tag ``0``. > > +Upgrading to stricter tag checking modes > +---------------------------------------- > + > +On some CPUs the performance of MTE in stricter tag checking modes > +is the same as that of less strict tag checking modes. This makes it > +worthwhile to enable stricter checks on those CPUs when a less strict > +checking mode is requested, in order to gain the error detection > +benefits of the stricter checks without the performance downsides. To > +opt into upgrading to a stricter checking mode on those CPUs, the user > +can set the ``PR_MTE_DYNAMIC_TCF`` flag bit in the ``flags`` argument > +to the ``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call. > + > +This feature is currently only supported for upgrading from > +asynchronous mode. To configure a CPU to upgrade from asynchronous mode > +to synchronous mode, a privileged user may write the value ``1`` to > +``/sys/devices/system/cpu/cpu/mte_upgrade_async``, and to disable > +upgrading they may write the value ``2``. By default the feature is > +disabled on all CPUs. Why not 0 to disable? This should be the default. I'd keep 2 for upgrading to the new asymmetric mode in v8.7 (reads sync, writes async). > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index b4bb67f17a2c..27a12c53529d 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -527,8 +527,19 @@ static void erratum_1418040_thread_switch(struct task_struct *prev, > write_sysreg(val, cntkctl_el1); > } > > -static void update_sctlr_el1(u64 sctlr) > +DECLARE_PER_CPU_READ_MOSTLY(u64, mte_upgrade_async); > + > +void update_sctlr_el1(u64 sctlr) > { > + if (sctlr & SCTLR_USER_DYNAMIC_TCF) { > + sctlr &= ~SCTLR_USER_DYNAMIC_TCF; > + > + if ((sctlr & SCTLR_EL1_TCF0_MASK) == SCTLR_EL1_TCF0_ASYNC) { > + sctlr &= ~SCTLR_EL1_TCF0_MASK; > + sctlr |= __this_cpu_read(mte_upgrade_async); > + } > + } I replied to your v2 already. I'd prefer this to be handled in mte.c. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel