Re: [PATCH v3] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis

From: Catalin Marinas <catalin.marinas@arm.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Will Deacon <will@kernel.org>,
	Evgenii Stepanov <eugenis@google.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis
Date: Mon, 14 Jun 2021 19:02:05 +0100	[thread overview]
Message-ID: <20210614180204.GJ30667@arm.com> (raw)
In-Reply-To: <20210614175609.GI30667@arm.com>

On Mon, Jun 14, 2021 at 06:56:09PM +0100, Catalin Marinas wrote:
> On Fri, Jun 11, 2021 at 02:51:01PM -0700, Peter Collingbourne wrote:
> > diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst
> > index b540178a93f8..2fc145de6530 100644
> > --- a/Documentation/arm64/memory-tagging-extension.rst
> > +++ b/Documentation/arm64/memory-tagging-extension.rst
> > @@ -120,6 +120,25 @@ in the ``PR_MTE_TAG_MASK`` bit-field.
> >  interface provides an include mask. An include mask of ``0`` (exclusion
> >  mask ``0xffff``) results in the CPU always generating tag ``0``.
> >  
> > +Upgrading to stricter tag checking modes
> > +----------------------------------------
> > +
> > +On some CPUs the performance of MTE in stricter tag checking modes
> > +is the same as that of less strict tag checking modes. This makes it
> > +worthwhile to enable stricter checks on those CPUs when a less strict
> > +checking mode is requested, in order to gain the error detection
> > +benefits of the stricter checks without the performance downsides. To
> > +opt into upgrading to a stricter checking mode on those CPUs, the user
> > +can set the ``PR_MTE_DYNAMIC_TCF`` flag bit in the ``flags`` argument
> > +to the ``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call.
> > +
> > +This feature is currently only supported for upgrading from
> > +asynchronous mode. To configure a CPU to upgrade from asynchronous mode
> > +to synchronous mode, a privileged user may write the value ``1`` to
> > +``/sys/devices/system/cpu/cpu<N>/mte_upgrade_async``, and to disable
> > +upgrading they may write the value ``2``. By default the feature is
> > +disabled on all CPUs.
> 
> Why not 0 to disable? This should be the default. I'd keep 2 for
> upgrading to the new asymmetric mode in v8.7 (reads sync, writes async).

Ah, I think I get it, you wanted to use the TCF values. Fine by me but
I'd actually still keep 0 for disable (which is the default value I
guess) with the 1 (or 3 later) for the upgrade. We may also add an
mte_upgrade_asym file at some point.

-- 
Catalin

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