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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ltUKl-006BNI-2p; Wed, 16 Jun 2021 12:07:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ltUKh-006BMc-5n for linux-arm-kernel@lists.infradead.org; Wed, 16 Jun 2021 12:07:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3B101042; Wed, 16 Jun 2021 05:07:42 -0700 (PDT) Received: from lpieralisi (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CC2D3F719; Wed, 16 Jun 2021 05:07:41 -0700 (PDT) Date: Wed, 16 Jun 2021 13:07:35 +0100 From: Lorenzo Pieralisi To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Catalin Marinas , Mark Rutland , Valentin Schneider , Alexandru Elisei , Russell King , kernel-team@android.com Subject: Re: [PATCH 1/3] arm64: Add cpuidle context save/restore helpers Message-ID: <20210616120735.GA31915@lpieralisi> References: <20210608172715.2396787-1-maz@kernel.org> <20210608172715.2396787-2-maz@kernel.org> <20210611164657.GA9252@lpieralisi> <87czsrthkv.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87czsrthkv.wl-maz@kernel.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210616_050747_353273_DDF543CB X-CRM114-Status: GOOD ( 27.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Jun 12, 2021 at 01:04:16PM +0100, Marc Zyngier wrote: > On Fri, 11 Jun 2021 17:46:57 +0100, > Lorenzo Pieralisi wrote: > > > > On Tue, Jun 08, 2021 at 06:27:13PM +0100, Marc Zyngier wrote: > > > As we need to start doing some additional work on all idle > > > paths, let's introduce a set of macros that will perform > > > the work related to the GICv3 pseudo-NMI idle entry exit. > > > > > > Stubs are introduced to 32bit ARM for compatibility. > > > As these helpers are currently unused, the is no functional > > > > s/the/there > > > > > change. > > > > > > Signed-off-by: Marc Zyngier > > > --- > > > arch/arm/include/asm/cpuidle.h | 5 +++++ > > > arch/arm64/include/asm/cpuidle.h | 35 ++++++++++++++++++++++++++++++++ > > > 2 files changed, 40 insertions(+) > > > > > > diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h > > > index 0d67ed682e07..1e0b8da12d96 100644 > > > --- a/arch/arm/include/asm/cpuidle.h > > > +++ b/arch/arm/include/asm/cpuidle.h > > > @@ -49,4 +49,9 @@ extern int arm_cpuidle_suspend(int index); > > > > > > extern int arm_cpuidle_init(int cpu); > > > > > > +struct arm_cpuidle_context { }; > > > + > > > +#define arm_cpuidle_save_context(c) (void)c > > > +#define arm_cpuidle_restore_context(c) (void)c > > > + > > > #endif > > > diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h > > > index 3c5ddb429ea2..53adad0a5c7e 100644 > > > --- a/arch/arm64/include/asm/cpuidle.h > > > +++ b/arch/arm64/include/asm/cpuidle.h > > > @@ -18,4 +18,39 @@ static inline int arm_cpuidle_suspend(int index) > > > return -EOPNOTSUPP; > > > } > > > #endif > > > + > > > +#ifdef CONFIG_ARM64_PSEUDO_NMI > > > +#include > > > + > > > +struct arm_cpuidle_context { > > > + unsigned long pmr; > > > + unsigned long daif_bits; > > > +}; > > > + > > > +#define arm_cpuidle_save_context(__c) \ > > > + do { \ > > > + struct arm_cpuidle_context *c = __c; \ > > > + if (system_uses_irq_prio_masking()) { \ > > > + c->daif_bits = read_sysreg(daif); \ > > > + write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \ > > > + daif); \ > > > + c->pmr = gic_read_pmr(); \ > > > + gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); \ > > > + } \ > > > + } while (0) > > > + > > > +#define arm_cpuidle_restore_context(__c) \ > > > + do { \ > > > + struct arm_cpuidle_context *c = __c; \ > > > + if (system_uses_irq_prio_masking()) { \ > > > + gic_write_pmr(c->pmr); \ > > > + write_sysreg(c->daif_bits, daif); \ > > > + } \ > > > + } while (0) > > > +#else > > > +struct arm_cpuidle_context { }; > > > + > > > +#define arm_cpuidle_save_context(c) (void)c > > > +#define arm_cpuidle_restore_context(c) (void)c > > > +#endif > > > #endif > > > > It looks good to me - maybe I would define it irq_context for clarity > > but that's just a naming convention. > > would: > > struct arm_cpuidle_irq_context { ... }; > #define arm_cpuidle_save_irq_context(c) ... > #define arm_cpuidle_restore_irq_context(c) ... > > be OK for you? Yes absolutely, thanks a lot. Lorenzo > > Reviewed-by: Lorenzo Pieralisi > > Thanks! > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel