From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B95C2C11F67 for ; Tue, 29 Jun 2021 15:56:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85CF961DBF for ; Tue, 29 Jun 2021 15:56:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85CF961DBF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rS2CtTrDB8W4bCxHrjVIQLNpIVNBKD4m4K38AU4PkPw=; b=ZgxKx3AvnHOaub ROlC8/upGn2aC66niGL2n64kGmxYdWASu1tZmxEEKiBtBSlvPE2xvK5xBxIoDxPlYtxnRdGffXthP qrhifFGfMsFoCcMftsvoK2ZxkUNj6CB8WUdyb1eg3iODUWfYxnSXruyMIDqFCuszbE2i0PcUhMa1z 5sneKJ+u0NSHgrCQn7PsrWBf5uIS2zTJ3f51PU8hataG7glE8qylaYSRfhIG9NAKGfi7lJ12Jd53r aluUwku1FnfOCluWOCM4w1knm1UPRoe66Kh/jhlXTU21oVgqNlXojTVhLv4miWPk/omxw4n375ihi dSptte7QsWSQhKku8EpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyG4j-00BX3o-Le; Tue, 29 Jun 2021 15:55:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyG4f-00BX34-Ng for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 15:54:59 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id CA3C961D4D; Tue, 29 Jun 2021 15:54:55 +0000 (UTC) Date: Tue, 29 Jun 2021 16:54:53 +0100 From: Catalin Marinas To: Tejas Belagod Cc: Szabolcs Nagy , Will Deacon , Peter Collingbourne , Vincenzo Frascino , Evgenii Stepanov , Linux ARM Subject: Re: [PATCH v5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Message-ID: <20210629155453.GD10900@arm.com> References: <20210624165228.GB25097@arm.com> <20210625092253.GJ13058@arm.com> <20210625120137.GC20835@arm.com> <20210625123959.GB3170@willie-the-truck> <20210625135350.GD20835@arm.com> <20210628101448.GA5503@willie-the-truck> <20210628152023.GA9308@arm.com> <20210629104625.GA7168@willie-the-truck> <20210629135831.GC14854@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_085457_847188_33D25835 X-CRM114-Status: GOOD ( 34.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jun 29, 2021 at 03:31:26PM +0100, Tejas Belagod wrote: > > The 06/29/2021 11:46, Will Deacon wrote: > > > On Mon, Jun 28, 2021 at 04:20:24PM +0100, Catalin Marinas wrote: > > > > Another option is a mapping table where async can be remapped to > > > > sync and sync to async (or even to "none" for both). That's not far > > > > from one of Peter's mte-upgrade-async proposal, we just add > > > > mte-map-async and mte-map-sync options. Most likely we'll just use > > > > mte-map-async for now to map it to sync on some CPUs but it wouldn't > > > > exclude other forced settings. > > > > > > Catalin and I discussed this offline and ended up with another option: > > > retrospectively change the prctl() ABI so that the 'flags' argument > > > accepts a bitmask of modes that the application is willing to accept. > > > This doesn't break any existing users, as we currently enforce that > > > only one mode is specified, but it would allow things like: > > > > > > prctl(PR_SET_TAGGED_ADDR_CTRL, > > > PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, > > > 0, 0, 0); > > > > > > which is actually very similar to Peter's PR_MTE_DYNAMIC_TCF proposal, > > > with the difference that I think this extends more naturally as new > > > PR_MTR_TCF_* flags are introduced. > > > > > > Then we expose a per-cpu file in sysfs (say "cpuX/mte_tcf_preferred") > > > which initially reads as "async". If the root user does, e.g. > > > > > > # echo "sync" > cpu1/mte_tcf_preferred > > > > > > then a task which has successfully issued a PR_SET_TAGGED_ADDR_CTRL > > > prctl() request for PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC will run in > > > sync mode on CPU1, but async mode on other CPUs (assuming they > > > retain the default value). > > > > > > We'll need to special-case PR_MTE_TCF_NONE, as that's just a shorthand > > > for "no flags" so doing PR_MTE_TCF_NONE | PR_MTE_TCF_SYNC is just the > > > same as doing PR_MTE_TCF_SYNC (which I think is already the behaviour > > > today). The only values which the sysfs files would accept today > > > are "sync" and "async". > > > > > > When faced with a situation where the prctl() flags for a task do not > > > intersect with the preferred mode for a CPU on which the task is going > > > to run, the lowest bit number flag is chosen from the mask set by the > > > prctl(). > > > > > > Thoughts? > > > > i'm happy with this. > > > > "lowest bit number" flag may not be optimal if there are many flags, > > but i don't expect many more tag check modes. > > > > no separate TCF_NONE bit means if we later want to turn tag check > > off per cpu there is no opt-out. but i guess this is fine. If some CPU in the system has an erratum that requires TCF_NONE, I'd rather disable MTE altogether (via a kernel patch). > > will armv8.7-a style asymmetric check use separate flag or TCF_SYNC > > | TCF_ASYNC may enable it? i see arguments either way. > > If app wants to say 'I want either TCF_SYNC | TCF_ASYNC, but not > TCF_ASYM' it will have to be a separate bit, right? Will and I talked about this as well and we decided that it's better to have a separate TCF_ASYM bit. So SYNC|ASYNC won't be "upgradable" to ASYM. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel