From: Leo Yan <leo.yan@linaro.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Leo Yan <leo.yan@linaro.org>
Subject: [PATCH 2/2] coresight: catu: Correct memory sync ranges in catu mode
Date: Sat, 10 Jul 2021 15:02:06 +0800 [thread overview]
Message-ID: <20210710070206.462875-2-leo.yan@linaro.org> (raw)
In-Reply-To: <20210710070206.462875-1-leo.yan@linaro.org>
Current code misses to handle the case for the trace wrapping around,
thus it fails to sync the complete memory ranges in catu mode.
This patch corrects the memory sync ranges, when detects the wrapping
around case, it splits into two chunks: one chunk is the tail of the
buffer and another chunk is from the start of the buffer after wrapping
around.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
drivers/hwtracing/coresight/coresight-catu.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
index e0740c6dbd54..634af451f0d3 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -323,7 +323,24 @@ static void catu_sync_etr_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
}
etr_buf->offset = r_offset;
- tmc_sg_table_sync_data_range(catu_table, r_offset, etr_buf->len);
+
+ if (r_offset + etr_buf->len > etr_buf->size) {
+ int len1, len2;
+
+ /*
+ * If trace data is wrapped around, sync AUX bounce buffer
+ * for two chunks: "len1" is for the trace date length at
+ * the tail of bounce buffer, and "len2" is the length from
+ * the start of the buffer after wrapping around.
+ */
+ len1 = etr_buf->size - r_offset;
+ len2 = etr_buf->len - len1;
+ tmc_sg_table_sync_data_range(catu_table, r_offset, len1);
+ tmc_sg_table_sync_data_range(catu_table, 0, len2);
+ } else {
+ tmc_sg_table_sync_data_range(catu_table, r_offset,
+ etr_buf->len);
+ }
}
static int catu_alloc_etr_buf(struct tmc_drvdata *tmc_drvdata,
--
2.25.1
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next prev parent reply other threads:[~2021-07-10 7:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-10 7:02 [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Leo Yan
2021-07-10 7:02 ` Leo Yan [this message]
2021-07-12 10:26 ` [PATCH 2/2] coresight: catu: Correct memory sync ranges in catu mode Suzuki K Poulose
2021-07-12 10:25 ` [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Suzuki K Poulose
2021-07-12 11:10 ` Leo Yan
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