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From: Leo Yan <leo.yan@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
	Mike Leach <mike.leach@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode
Date: Mon, 12 Jul 2021 19:10:14 +0800	[thread overview]
Message-ID: <20210712111014.GC704210@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <3038eb59-155c-5c3d-18e3-e45e56b52523@arm.com>

On Mon, Jul 12, 2021 at 11:25:54AM +0100, Suzuki Kuruppassery Poulose wrote:
> Hi Leo,
> 
> On 10/07/2021 08:02, Leo Yan wrote:
> > Current code syncs the buffer range is [offset, offset+len), it doesn't
> > consider the case when the trace data is wrapped around, in this case
> > 'offset+len' is bigger than 'etr_buf->size'.  Thus it syncs buffer out
> > of the memory buffer, and it also misses to sync buffer from the start
> > of the memory.
> > 
> 
> I doubt this claim is valid. We do the sync properly, taking the page
> corresponding to the "offset" wrapping it around in "page" index.
> 
> Here is the code :
> 
> 
> 
> void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
>                                   u64 offset, u64 size)
> {
>         int i, index, start;
>         int npages = DIV_ROUND_UP(size, PAGE_SIZE);
>         struct device *real_dev = table->dev->parent;
>         struct tmc_pages *data = &table->data_pages;
> 
>         start = offset >> PAGE_SHIFT;
>         for (i = start; i < (start + npages); i++) {
>                 index = i % data->nr_pages;
>                 dma_sync_single_for_cpu(real_dev, data->daddrs[index],
>                                         PAGE_SIZE, DMA_FROM_DEVICE);
>         }
> }
> 
> 
> See that the npages accounts for the "size" requested and we wrap the
> "index" by the total number of pages in the buffer and pick the right
> page.
> 
> So, I think this fix is not needed.

Ouch, you are right :)  Let's drop these two patches.

Thanks,
Leo

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      reply	other threads:[~2021-07-12 11:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-10  7:02 [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Leo Yan
2021-07-10  7:02 ` [PATCH 2/2] coresight: catu: Correct memory sync ranges in catu mode Leo Yan
2021-07-12 10:26   ` Suzuki K Poulose
2021-07-12 10:25 ` [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Suzuki K Poulose
2021-07-12 11:10   ` Leo Yan [this message]

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