From: Leo Yan <leo.yan@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
Mike Leach <mike.leach@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] coresight: tmc-etr: Speed up for bounce buffer in flat mode
Date: Mon, 12 Jul 2021 19:36:46 +0800 [thread overview]
Message-ID: <20210712113646.GD704210@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <5f3148bf-3efa-5866-b426-8bab4eb40282@arm.com>
On Mon, Jul 12, 2021 at 12:17:04PM +0100, Suzuki Kuruppassery Poulose wrote:
[...]
> > I am doubt why you conclude "always start tracing at the beginning of
> > the buffer"? I read the driver but cannot find any code in the driver
> > to reset rrp and rwp after fetching the trace data, or there have any
> > implict operation to reset pointers?
>
> The ETR is always programmed with the base address of the "ETR" buffer,
> which is *not the same* as the perf ring buffer, since we always do
> double buffering. We do not program the RRP/RWP of the ETR (except
> for the SoC-600, where it is mandatory and we set them to the base
> address). Thus there is no context associated with the ETR buffer.
> But at the end of the run, we do read the RRP/ RWP to figure out
> where the ETR has reached.
>
> As for reseting the RRP / RWP, at the beginning of a session, is
> done implicitly for the ETR (except for SoC-600 ETRs as explained
> above) by the hardware to the base address.
Yes, I finally matched your description with the code. Will respin
patch for this.
Thanks for confirmation!
Leo
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prev parent reply other threads:[~2021-07-12 11:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-10 7:01 [PATCH v2] coresight: tmc-etr: Speed up for bounce buffer in flat mode Leo Yan
2021-07-12 9:55 ` Suzuki K Poulose
2021-07-12 11:09 ` Leo Yan
2021-07-12 11:17 ` Suzuki K Poulose
2021-07-12 11:36 ` Leo Yan [this message]
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