From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B2A6C07E9A for ; Wed, 14 Jul 2021 14:06:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C593D613C9 for ; Wed, 14 Jul 2021 14:06:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C593D613C9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=H74t6U2XsO5Ct4UUb90ChCGrnL+71z/h0mPLsh4l8Bs=; b=ZJXksaWPrsgBlW 27kKf2sZvO1kR7EFuJ148Gxhaw/eIQIZrjhBah1UG5vS/kM8f3q1ShtOvYrcegtjdMnvlwz2nA0/4 tLd7QwwpKhyA3wm4nJs+o9niqZ8k0bNB938D3u3viqR4T0sAZMbny7W8mmY3CvAPM8fRNFkYsr/XZ +TYjZpmvSPKwRSF8j8tfl/+FIzCVKbiGuZ8jjhgzgyS+M32NHSQYS5WTS6/VpBEjEzs4ex5U+UK6Y m/TfczEdPgIewbgrnNXui4xYBkAlBytP6Od13rbZFMTA7FXKINZmB/DJk99qdTmb6X2rdO6ay2S9W saI75raf8WFgl+Epey9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3fVd-00Dnni-HJ; Wed, 14 Jul 2021 14:05:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3fVU-00DnkJ-4s for linux-arm-kernel@lists.infradead.org; Wed, 14 Jul 2021 14:05:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94F9E31B; Wed, 14 Jul 2021 07:04:56 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.2.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B5FD63F694; Wed, 14 Jul 2021 07:04:54 -0700 (PDT) Date: Wed, 14 Jul 2021 15:04:42 +0100 From: Mark Rutland To: Peter Collingbourne Cc: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit Message-ID: <20210714140442.GA28555@C02TD0UTHF1T.local> References: <20210714013638.3995315-1-pcc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210714013638.3995315-1-pcc@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210714_070500_315617_94F894F1 X-CRM114-Status: GOOD ( 18.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Peter, On Tue, Jul 13, 2021 at 06:36:38PM -0700, Peter Collingbourne wrote: > Accessing GCR_EL1 and issuing an ISB can be expensive on some > microarchitectures. Although we must write to GCR_EL1, we can > restructure the code to avoid reading from it because the new value > can be derived entirely from the exclusion mask, which is already in > a GPR. Do so. > > Signed-off-by: Peter Collingbourne > Link: https://linux-review.googlesource.com/id/I560a190a74176ca4cc5191dad08f77f6b1577c75 > --- > v4: > - split in two > > v3: > - go back to modifying on entry/exit; optimize that path instead > > v2: > - rebase onto v9 of the tag checking mode preference series > > arch/arm64/kernel/entry.S | 12 ++++-------- > 1 file changed, 4 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index ce59280355c5..2d6dc62d929a 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -175,15 +175,11 @@ alternative_else_nop_endif > #endif > .endm > > - .macro mte_set_gcr, tmp, tmp2 > + .macro mte_set_gcr, mte_ctrl, tmp > #ifdef CONFIG_ARM64_MTE > - /* > - * Calculate and set the exclude mask preserving > - * the RRND (bit[16]) setting. > - */ > - mrs_s \tmp2, SYS_GCR_EL1 > - bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 > - msr_s SYS_GCR_EL1, \tmp2 > + ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 > + orr \tmp, \tmp, #SYS_GCR_EL1_RRND > + msr_s SYS_GCR_EL1, \tmp > #endif > .endm Since the mte_ctrl value only has the Exclude bits set, we can make this even simpler: orr \tmp, \mte_ctrl, #SYS_GCR_EL1_RRND msr_s SYS_GCR_EL1, \tmp Otherwise, looks good to me! Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel