[PATCH v3 03/12] dt-bindings: mediatek: display: add MERGE additional description

[jason-jh.lin <jason-jh.lin@mediatek.com>]

1. clock drivers of MERGE
   The MERGE controller may have 2 clock inputs.
   The second clock of MERGE is async clock which is controlling
   the async buffer between MERGE and other display function blocks.

2. MERGE fifo settings enable
   The setting of merge fifo is mainly provided for the display
   latency buffer. To ensure that the back-end panel display data
   will not be underrun, a little more data is needed in the fifo.
   According to the merge fifo settings, when the water level is
   detected to be insufficient, it will trigger RDMA sending
   ultra and preulra command to SMI to speed up the data rate.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,disp.yaml     | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index 910bb9ce61d6..8beeb9c3c057 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -237,6 +237,9 @@ properties:
     description: clock drivers
       See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
       For most function blocks this is just a single clock input.
+      The MERGE controller may have 2 clock inputs. The second clock of MERGE is async clock,
+      which is controlling the synchronous process between MERGE and other display function
+      blocks cross clock domain.
       Only the DSI and DPI controller nodes have multiple clock inputs. These are documented
       in mediatek,dsi.txt and mediatek,dpi.yaml, respectively.
       An exception is that the mt8183 mutex is always free running with no clocks property.
@@ -270,6 +273,15 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     enum: [8*1024, 5*1024, 2*1024]
 
+  mediatek,merge-fifo-en:
+    description: MERGE fifo settings enable
+      The setting of merge fifo is mainly provided for the display latency buffer.
+      To ensure that the back-end panel display data will not be underrun,
+      a little more data is needed in the fifo. According to the merge fifo settings,
+      when the water level is detected to be insufficient, it will trigger RDMA sending
+      ultra and preulra command to SMI to speed up the data rate.
+    type: boolean
+
   power-domains:
     description: A phandle and PM domain specifier as defined by bindings of
       the power controller specified by phandle. See
-- 
2.18.0
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